TW200512791A - Etching method - Google Patents
Etching methodInfo
- Publication number
- TW200512791A TW200512791A TW093121953A TW93121953A TW200512791A TW 200512791 A TW200512791 A TW 200512791A TW 093121953 A TW093121953 A TW 093121953A TW 93121953 A TW93121953 A TW 93121953A TW 200512791 A TW200512791 A TW 200512791A
- Authority
- TW
- Taiwan
- Prior art keywords
- pattern width
- mask layer
- pattern
- region
- belonging
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003337373 | 2003-09-29 | ||
JP2004188013A JP4727171B2 (ja) | 2003-09-29 | 2004-06-25 | エッチング方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200512791A true TW200512791A (en) | 2005-04-01 |
TWI357092B TWI357092B (zh) | 2012-01-21 |
Family
ID=34380387
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093121953A TW200512791A (en) | 2003-09-29 | 2004-07-22 | Etching method |
Country Status (5)
Country | Link |
---|---|
US (1) | US7256135B2 (zh) |
JP (1) | JP4727171B2 (zh) |
KR (1) | KR100619111B1 (zh) |
CN (1) | CN1300637C (zh) |
TW (1) | TW200512791A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI475335B (zh) * | 2011-03-29 | 2015-03-01 | Fujifilm Corp | 抗蝕劑圖案形成方法以及使用該抗蝕劑圖案的圖案化基板的製造方法 |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7723238B2 (en) * | 2004-06-16 | 2010-05-25 | Tokyo Electron Limited | Method for preventing striation at a sidewall of an opening of a resist during an etching process |
US7271107B2 (en) * | 2005-02-03 | 2007-09-18 | Lam Research Corporation | Reduction of feature critical dimensions using multiple masks |
US7539969B2 (en) * | 2005-05-10 | 2009-05-26 | Lam Research Corporation | Computer readable mask shrink control processor |
US7465525B2 (en) * | 2005-05-10 | 2008-12-16 | Lam Research Corporation | Reticle alignment and overlay for multiple reticle process |
US20060292876A1 (en) * | 2005-06-21 | 2006-12-28 | Tokyo Electron Limited | Plasma etching method and apparatus, control program and computer-readable storage medium |
US7271108B2 (en) * | 2005-06-28 | 2007-09-18 | Lam Research Corporation | Multiple mask process with etch mask stack |
US7273815B2 (en) * | 2005-08-18 | 2007-09-25 | Lam Research Corporation | Etch features with reduced line edge roughness |
US20070211402A1 (en) * | 2006-03-08 | 2007-09-13 | Tokyo Electron Limited | Substrate processing apparatus, substrate attracting method, and storage medium |
JP2007294905A (ja) * | 2006-03-30 | 2007-11-08 | Hitachi High-Technologies Corp | 半導体製造方法およびエッチングシステム |
JP4861893B2 (ja) * | 2006-07-28 | 2012-01-25 | 東京エレクトロン株式会社 | 基板の処理方法、プログラム、コンピュータ記憶媒体及び基板の処理システム |
US7491343B2 (en) * | 2006-09-14 | 2009-02-17 | Lam Research Corporation | Line end shortening reduction during etch |
JP2008078582A (ja) * | 2006-09-25 | 2008-04-03 | Hitachi High-Technologies Corp | プラズマエッチング方法 |
JP4912907B2 (ja) * | 2007-02-06 | 2012-04-11 | 東京エレクトロン株式会社 | プラズマエッチング方法及びプラズマエッチング装置 |
JP5065787B2 (ja) * | 2007-07-27 | 2012-11-07 | 東京エレクトロン株式会社 | プラズマエッチング方法、プラズマエッチング装置、および記憶媒体 |
US7838426B2 (en) * | 2007-08-20 | 2010-11-23 | Lam Research Corporation | Mask trimming |
US7998872B2 (en) * | 2008-02-06 | 2011-08-16 | Tokyo Electron Limited | Method for etching a silicon-containing ARC layer to reduce roughness and CD |
JP2009193988A (ja) * | 2008-02-12 | 2009-08-27 | Tokyo Electron Ltd | プラズマエッチング方法及びコンピュータ記憶媒体 |
JP5027753B2 (ja) * | 2008-07-30 | 2012-09-19 | 東京エレクトロン株式会社 | 基板処理制御方法及び記憶媒体 |
JP4638550B2 (ja) | 2008-09-29 | 2011-02-23 | 東京エレクトロン株式会社 | マスクパターンの形成方法、微細パターンの形成方法及び成膜装置 |
US9601349B2 (en) * | 2009-02-17 | 2017-03-21 | Macronix International Co., Ltd. | Etching method |
JP5260356B2 (ja) | 2009-03-05 | 2013-08-14 | 東京エレクトロン株式会社 | 基板処理方法 |
CN102117737B (zh) * | 2009-12-30 | 2015-01-07 | 中国科学院微电子研究所 | 减小半导体器件中ler的方法及半导体器件 |
JP2013222852A (ja) | 2012-04-17 | 2013-10-28 | Tokyo Electron Ltd | 有機膜をエッチングする方法及びプラズマエッチング装置 |
JP6355374B2 (ja) * | 2013-03-22 | 2018-07-11 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP6289996B2 (ja) * | 2014-05-14 | 2018-03-07 | 東京エレクトロン株式会社 | 被エッチング層をエッチングする方法 |
JP6817168B2 (ja) * | 2017-08-25 | 2021-01-20 | 東京エレクトロン株式会社 | 被処理体を処理する方法 |
JP6913569B2 (ja) | 2017-08-25 | 2021-08-04 | 東京エレクトロン株式会社 | 被処理体を処理する方法 |
US11227767B2 (en) | 2018-05-03 | 2022-01-18 | Tokyo Electron Limited | Critical dimension trimming method designed to minimize line width roughness and line edge roughness |
JP7066565B2 (ja) * | 2018-07-27 | 2022-05-13 | 東京エレクトロン株式会社 | プラズマ処理方法およびプラズマ処理装置 |
JP7278456B2 (ja) * | 2018-07-27 | 2023-05-19 | 東京エレクトロン株式会社 | プラズマ処理装置 |
JP7195113B2 (ja) * | 2018-11-07 | 2022-12-23 | 東京エレクトロン株式会社 | 処理方法及び基板処理装置 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE68923247T2 (de) * | 1988-11-04 | 1995-10-26 | Fujitsu Ltd | Verfahren zum Erzeugen eines Fotolackmusters. |
JP3445886B2 (ja) * | 1995-10-27 | 2003-09-08 | 松下電器産業株式会社 | 半導体装置の製造方法及び半導体装置の製造装置 |
JP3316407B2 (ja) * | 1997-02-26 | 2002-08-19 | シャープ株式会社 | 半導体装置の製造方法 |
US6635185B2 (en) * | 1997-12-31 | 2003-10-21 | Alliedsignal Inc. | Method of etching and cleaning using fluorinated carbonyl compounds |
JP2000077386A (ja) * | 1998-08-27 | 2000-03-14 | Seiko Epson Corp | パターン形成方法 |
US6362111B1 (en) * | 1998-12-09 | 2002-03-26 | Texas Instruments Incorporated | Tunable gate linewidth reduction process |
JP2000183027A (ja) * | 1998-12-11 | 2000-06-30 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
TW525260B (en) * | 1999-08-02 | 2003-03-21 | Taiwan Semiconductor Mfg | Shallow trench isolation pull-back process |
US6461969B1 (en) * | 1999-11-22 | 2002-10-08 | Chartered Semiconductor Manufacturing Ltd. | Multiple-step plasma etching process for silicon nitride |
US6569774B1 (en) * | 2000-08-31 | 2003-05-27 | Micron Technology, Inc. | Method to eliminate striations and surface roughness caused by dry etch |
JP2002343780A (ja) * | 2001-05-01 | 2002-11-29 | Applied Materials Inc | ガス導入装置、成膜装置、及び成膜方法 |
CN1277293C (zh) * | 2001-07-10 | 2006-09-27 | 东京毅力科创株式会社 | 干蚀刻方法 |
JP2003077900A (ja) * | 2001-09-06 | 2003-03-14 | Hitachi Ltd | 半導体装置の製造方法 |
US20040097077A1 (en) * | 2002-11-15 | 2004-05-20 | Applied Materials, Inc. | Method and apparatus for etching a deep trench |
US20040224524A1 (en) * | 2003-05-09 | 2004-11-11 | Applied Materials, Inc. | Maintaining the dimensions of features being etched on a lithographic mask |
US6955961B1 (en) * | 2004-05-27 | 2005-10-18 | Macronix International Co., Ltd. | Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution |
-
2004
- 2004-06-25 JP JP2004188013A patent/JP4727171B2/ja not_active Expired - Fee Related
- 2004-07-22 TW TW093121953A patent/TW200512791A/zh unknown
- 2004-09-15 KR KR1020040073632A patent/KR100619111B1/ko active IP Right Grant
- 2004-09-20 US US10/943,983 patent/US7256135B2/en active Active
- 2004-09-29 CN CNB2004100806705A patent/CN1300637C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI475335B (zh) * | 2011-03-29 | 2015-03-01 | Fujifilm Corp | 抗蝕劑圖案形成方法以及使用該抗蝕劑圖案的圖案化基板的製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1300637C (zh) | 2007-02-14 |
JP2005129893A (ja) | 2005-05-19 |
TWI357092B (zh) | 2012-01-21 |
CN1603959A (zh) | 2005-04-06 |
US20050070111A1 (en) | 2005-03-31 |
US7256135B2 (en) | 2007-08-14 |
KR20050031375A (ko) | 2005-04-06 |
KR100619111B1 (ko) | 2006-09-04 |
JP4727171B2 (ja) | 2011-07-20 |
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