JP6913569B2 - 被処理体を処理する方法 - Google Patents
被処理体を処理する方法 Download PDFInfo
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- JP6913569B2 JP6913569B2 JP2017162600A JP2017162600A JP6913569B2 JP 6913569 B2 JP6913569 B2 JP 6913569B2 JP 2017162600 A JP2017162600 A JP 2017162600A JP 2017162600 A JP2017162600 A JP 2017162600A JP 6913569 B2 JP6913569 B2 JP 6913569B2
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- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
Description
このように、第1シーケンスが繰り返し実行されるので、比較的に薄い膜厚の膜を第1工程において形成し第1シーケンスを繰り返し実行することによって最終的に所望とする膜厚の膜を形成することができる。これにより、ホール幅の比較的に狭いホールにおいて、第1工程によって形成される膜によってホールの開口が閉塞される事態が十分に回避され得る。
比較的にホール幅が狭く第1工程で比較的に膜厚の薄い膜が形成されたホール(第1ホールという)において第2の膜が第2工程で除去されても、この時点において、比較的にホール幅が広く第1工程で比較的に膜厚の厚い膜が形成されたホール(第2ホールという)では第2の膜の一部が残存し得る。このような状態から、第2工程におけるエッチングが更に継続して行われる場合、第1の膜のエッチング耐性が第2の膜のエッチング耐性よりも低いので、第1ホールの方が第2ホールよりも速くエッチングが進行する。従って、比較的にエッチング耐性の低い第1の膜と比較的にエッチング耐性の高い第2の膜とを用いることによって、第1ホールと第2ホールとの間のホール幅のバラツキがより効果的に低減され得る。
Claims (12)
- 被処理体を処理する方法であって、
複数のホールが表面に設けられた被処理体を提供する工程と、
プラズマCVDにより前記ホールの内面に膜を形成する工程と、
前記膜を等方的にエッチングする工程と、
を含み、
エッチングする前記工程は、
窒素を含む第1のガスからプラズマを生成し、前記ホールの内面に混合層を形成する工程と、
次いで、フッ素を含む第2のガスからプラズマを生成し、前記混合層を除去する工程と、
を繰り返して、前記膜を等方的にエッチングする、
方法。 - 膜を形成する前記工程とエッチングする前記工程とは、繰り返し実行される、
請求項1に記載の方法。 - 前記第2のガスは、NF3ガスおよびO2ガスを含む、
請求項1に記載の方法。 - 前記第2のガスは、NF3ガス、O2ガス、H2ガスおよびArガスを含む、
請求項1に記載の方法。 - 前記第2のガスは、CH3Fガス、O2ガスおよびArガスを含む、
請求項1に記載の方法。 - 膜を形成する前記工程は、
前記ホールの内面に第1の膜を形成する段階と、
前記第1の膜上に第2の膜を形成する段階と、
を備え、
エッチングする前記工程における前記第1の膜のエッチング耐性は、前記第2の膜のエッチング耐性よりも低い、
請求項1から5の何れか一項に記載の方法。 - 第1の膜を形成する前記段階は、
前記被処理体にアミノシラン系ガスを吸着させることと、
酸素を含むガスからプラズマを生成することと、を繰り返すこと、
を含み、
第2の膜を形成する前記段階は、プラズマCVDにより該第2の膜を形成する、
請求項6に記載の方法。 - 被処理体を処理する方法であって、
被処理体を提供する工程であって、該被処理体には複数のホールが表面に設けられており、該複数のホールは第1のホール幅を有する第1のホール及び該第1のホール幅よりも大きい第2のホール幅を有する第2のホールを含む、該工程と、
前記被処理体にシーケンスを実行する工程と、
を備え、
前記シーケンスは、
前記複数のホールのそれぞれの内面に膜を形成する工程であって、前記第1のホールに形成される該膜の厚さが前記第2のホールに形成される該膜の厚さよりも小さくなるように該膜を形成する、該工程と、
前記膜を等方的にエッチングする工程であって、該エッチング後における前記第1のホール幅と前記第2のホール幅との差は、膜を形成する前記工程の開始時における該第1のホール幅と該第2のホール幅との差よりも小さく、該エッチング後における該第1のホール幅及び該第2のホール幅のそれぞれは、膜を形成する該工程の開始時における該第1のホール幅及び該第2のホール幅のそれぞれよりも狭い、該工程と、
を含む、
方法。 - 被処理体を処理する方法であって、
被処理体を提供する工程であって、該被処理体には複数のホールが表面に設けられており、該複数のホールは第1のホール幅を有する第1のホール及び該第1のホール幅よりも大きい第2のホール幅を有する第2のホールを含む、該工程と、
前記被処理体にシーケンスを実行する工程と、
を備え、
前記シーケンスは、
前記複数のホールのそれぞれの内面に膜を形成する工程であって、前記第1のホールに形成される該膜の厚さが前記第2のホールに形成される該膜の厚さよりも小さくなるように該膜を形成する、該工程と、
前記膜を等方的にエッチングする工程であって、該エッチング後における前記第1のホール幅と前記第2のホール幅との差は、膜を形成する前記工程の開始時における該第1のホール幅と該第2のホール幅との差よりも小さい、該工程と、
を含む、
方法(ただし、前記エッチング後において相互に隣接するホール間の距離が前記被処理体内で均一になる場合を除く)。 - 膜を形成する前記工程は、プラズマCVDによる成膜処理を含む、
請求項8または9に記載の方法。 - 前記膜は、シリコンを含有する、
請求項8から10の何れか一項に記載の方法。 - 前記シーケンスは、繰り返し実行される、
請求項8から11の何れか一項に記載の方法。
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