SG90205A1 - Process for producing semiconductor device - Google Patents

Process for producing semiconductor device

Info

Publication number
SG90205A1
SG90205A1 SG200006870A SG200006870A SG90205A1 SG 90205 A1 SG90205 A1 SG 90205A1 SG 200006870 A SG200006870 A SG 200006870A SG 200006870 A SG200006870 A SG 200006870A SG 90205 A1 SG90205 A1 SG 90205A1
Authority
SG
Singapore
Prior art keywords
wafer
adhesive layer
dicing
die bond
individual chips
Prior art date
Application number
SG200006870A
Other languages
English (en)
Inventor
Sugino Takashi
Senoo Hideo
Original Assignee
Lintec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lintec Corp filed Critical Lintec Corp
Publication of SG90205A1 publication Critical patent/SG90205A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043Making grooves, e.g. cutting
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
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    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2224/741Apparatus for manufacturing means for bonding, e.g. connectors
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Die Bonding (AREA)
SG200006870A 1999-11-30 2000-11-28 Process for producing semiconductor device SG90205A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34033499A JP4409014B2 (ja) 1999-11-30 1999-11-30 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
SG90205A1 true SG90205A1 (en) 2002-07-23

Family

ID=18335954

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200006870A SG90205A1 (en) 1999-11-30 2000-11-28 Process for producing semiconductor device

Country Status (10)

Country Link
US (1) US6656819B1 (ja)
EP (1) EP1107299B1 (ja)
JP (1) JP4409014B2 (ja)
KR (1) KR100655035B1 (ja)
CN (1) CN1168132C (ja)
DE (1) DE60028912T2 (ja)
HK (1) HK1035261A1 (ja)
MY (1) MY125340A (ja)
SG (1) SG90205A1 (ja)
TW (1) TW487981B (ja)

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JP2003045901A (ja) * 2001-08-01 2003-02-14 Sony Corp 素子の転写方法及びこれを用いた素子の配列方法、画像表示装置の製造方法
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WO2004047057A1 (ja) * 2002-11-19 2004-06-03 Ishikawa Seisakusho,Ltd. 画素制御素子の選択転写方法、画素制御素子の選択転写方法に使用される画素制御素子の実装装置、画素制御素子転写後の配線形成方法、及び、平面ディスプレイ基板
JP4599075B2 (ja) * 2003-03-26 2010-12-15 株式会社東芝 半導体製造装置及び半導体装置の製造方法
JP2004311576A (ja) * 2003-04-03 2004-11-04 Toshiba Corp 半導体装置の製造方法
JP2004319045A (ja) * 2003-04-18 2004-11-11 Lintec Corp 光ディスク製造用シートおよび光ディスク
JP4234630B2 (ja) * 2003-05-29 2009-03-04 古河電気工業株式会社 貫通構造を有する薄膜化回路基板の製造方法と保護用粘着テープ
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JP2005019571A (ja) * 2003-06-24 2005-01-20 Canon Inc チップの実装方法及び実装基板の製造装置
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JP4791843B2 (ja) * 2006-02-14 2011-10-12 株式会社ディスコ 接着フィルム付きデバイスの製造方法
JP4874769B2 (ja) * 2006-11-14 2012-02-15 株式会社東芝 表面保護テープ及びこの表面保護テープを用いた半導体装置の製造方法
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JP5426314B2 (ja) * 2009-10-19 2014-02-26 株式会社ディスコ 半導体デバイスの製造方法
KR101221871B1 (ko) * 2009-12-07 2013-01-15 한국전자통신연구원 반도체 소자의 제조방법
CN102244039B (zh) * 2010-05-11 2014-02-05 扬州杰利半导体有限公司 一种半导体晶片的裂片方法
JP5158896B2 (ja) * 2010-08-09 2013-03-06 古河電気工業株式会社 半導体チップの製造方法
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JP5976326B2 (ja) 2012-01-25 2016-08-23 日東電工株式会社 半導体装置の製造方法、及び、当該半導体装置の製造方法に用いられる接着フィルム
KR101327528B1 (ko) * 2012-06-14 2013-11-08 주식회사 케이엔제이 웨이퍼 칩 연마방법
JP2014033177A (ja) * 2012-07-12 2014-02-20 Denso Corp 半導体装置の製造方法
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