SG11201906017UA - Support for a semiconductor structure - Google Patents
Support for a semiconductor structureInfo
- Publication number
- SG11201906017UA SG11201906017UA SG11201906017UA SG11201906017UA SG11201906017UA SG 11201906017U A SG11201906017U A SG 11201906017UA SG 11201906017U A SG11201906017U A SG 11201906017UA SG 11201906017U A SG11201906017U A SG 11201906017UA SG 11201906017U A SG11201906017U A SG 11201906017UA
- Authority
- SG
- Singapore
- Prior art keywords
- international
- bernin
- chemin
- des
- pct
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 abstract 1
- 230000008520 organization Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1750646A FR3062238A1 (fr) | 2017-01-26 | 2017-01-26 | Support pour une structure semi-conductrice |
| PCT/EP2018/050677 WO2018137937A1 (fr) | 2017-01-26 | 2018-01-11 | Support pour une structure semiconductrice |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11201906017UA true SG11201906017UA (en) | 2019-08-27 |
Family
ID=59253590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11201906017UA SG11201906017UA (en) | 2017-01-26 | 2018-01-11 | Support for a semiconductor structure |
Country Status (9)
| Country | Link |
|---|---|
| US (2) | US11373856B2 (fr) |
| EP (1) | EP3574519B1 (fr) |
| JP (1) | JP2020505769A (fr) |
| KR (1) | KR20190108138A (fr) |
| CN (1) | CN110199375A (fr) |
| FR (1) | FR3062238A1 (fr) |
| SG (1) | SG11201906017UA (fr) |
| TW (1) | TW201841341A (fr) |
| WO (1) | WO2018137937A1 (fr) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3062517B1 (fr) * | 2017-02-02 | 2019-03-15 | Soitec | Structure pour application radiofrequence |
| FR3098342B1 (fr) | 2019-07-02 | 2021-06-04 | Soitec Silicon On Insulator | structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF |
| CN110687138B (zh) * | 2019-09-05 | 2022-08-05 | 长江存储科技有限责任公司 | 半导体结构的测量与边界特征提取方法及其装置 |
| FR3104322B1 (fr) * | 2019-12-05 | 2023-02-24 | Soitec Silicon On Insulator | Procédé de formation d'un substrat de manipulation pour une structure composite ciblant des applications rf |
| US20230230874A1 (en) | 2020-07-28 | 2023-07-20 | Soitec | Method for transferring a thin layer onto a support substrate provided with a charge-trapping layer |
| FR3113184B1 (fr) * | 2020-07-28 | 2022-09-16 | Soitec Silicon On Insulator | Procede de preparation d’un substrat support, et procede de report d’une couche mince sur ce substrat support |
| US11522516B2 (en) | 2020-08-27 | 2022-12-06 | RF360 Europe GmbH | Thin-film surface-acoustic-wave filter using lithium niobate |
| CN116783719A (zh) * | 2020-12-31 | 2023-09-19 | 华为技术有限公司 | 一种集成电路、功率放大器及电子设备 |
| FR3127588A1 (fr) | 2021-09-28 | 2023-03-31 | Lynred | Procede de realisation d’au moins une fenetre optique, fenetre optique et detecteur infrarouge associes |
| FR3138239B1 (fr) * | 2022-07-19 | 2024-06-21 | Soitec Silicon On Insulator | Procédé de fabrication d’un substrat support pour application radiofréquences |
Family Cites Families (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US347597A (en) * | 1886-08-17 | habyey | ||
| US6910A (en) * | 1849-11-27 | Abraham johnson and henry johnson | ||
| US269976A (en) * | 1883-01-02 | John watters | ||
| WO2000055397A1 (fr) | 1999-03-16 | 2000-09-21 | Shin-Etsu Handotai Co., Ltd. | Procede de production d'une tranche de silicium et tranche de silicium ainsi obtenue |
| AU2001257359A1 (en) | 2000-04-27 | 2001-11-07 | Verion Inc. | Zero order release and temperature-controlled microcapsules and process for the preparation thereof |
| FR2838865B1 (fr) | 2002-04-23 | 2005-10-14 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee |
| US20070032040A1 (en) * | 2003-09-26 | 2007-02-08 | Dimitri Lederer | Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses |
| FR2860341B1 (fr) | 2003-09-26 | 2005-12-30 | Soitec Silicon On Insulator | Procede de fabrication de structure multicouche a pertes diminuees |
| FR2880189B1 (fr) | 2004-12-24 | 2007-03-30 | Tracit Technologies Sa | Procede de report d'un circuit sur un plan de masse |
| FR2933233B1 (fr) * | 2008-06-30 | 2010-11-26 | Soitec Silicon On Insulator | Substrat de haute resistivite bon marche et procede de fabrication associe |
| US8252653B2 (en) * | 2008-10-21 | 2012-08-28 | Applied Materials, Inc. | Method of forming a non-volatile memory having a silicon nitride charge trap layer |
| FR2953640B1 (fr) | 2009-12-04 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante |
| CN103348473B (zh) | 2010-12-24 | 2016-04-06 | 斯兰纳半导体美国股份有限公司 | 用于半导体装置的富陷阱层 |
| FR2973158B1 (fr) * | 2011-03-22 | 2014-02-28 | Soitec Silicon On Insulator | Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences |
| US8772059B2 (en) * | 2011-05-13 | 2014-07-08 | Cypress Semiconductor Corporation | Inline method to monitor ONO stack quality |
| FR2985812B1 (fr) | 2012-01-16 | 2014-02-07 | Soitec Silicon On Insulator | Procede et dispositif de test de substrats semi-conducteurs pour applications radiofrequences |
| JP5978986B2 (ja) * | 2012-12-26 | 2016-08-24 | 信越半導体株式会社 | 高周波半導体装置及び高周波半導体装置の製造方法 |
| US9601591B2 (en) * | 2013-08-09 | 2017-03-21 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US9768056B2 (en) | 2013-10-31 | 2017-09-19 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition |
| US9299736B2 (en) | 2014-03-28 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding with uniform pattern density |
| FR3019373A1 (fr) * | 2014-03-31 | 2015-10-02 | St Microelectronics Sa | Procede de fabrication d'une plaque de semi-conducteur adaptee pour la fabrication d'un substrat soi et plaque de substrat ainsi obtenue |
| FR3024587B1 (fr) * | 2014-08-01 | 2018-01-26 | Soitec | Procede de fabrication d'une structure hautement resistive |
| US9853133B2 (en) * | 2014-09-04 | 2017-12-26 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity silicon-on-insulator substrate |
| WO2016081313A1 (fr) * | 2014-11-18 | 2016-05-26 | Sunedison Semiconductor Limited | Procédé de fabrication de plaquettes de semi-conducteur sur isolant à haute résistivité comprenant couches de piégeage de charges |
| FR3029682B1 (fr) * | 2014-12-04 | 2017-12-29 | Soitec Silicon On Insulator | Substrat semi-conducteur haute resistivite et son procede de fabrication |
| US10006910B2 (en) * | 2014-12-18 | 2018-06-26 | Agilome, Inc. | Chemically-sensitive field effect transistors, systems, and methods for manufacturing and using the same |
| US9618474B2 (en) * | 2014-12-18 | 2017-04-11 | Edico Genome, Inc. | Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids |
| US10283402B2 (en) * | 2015-03-03 | 2019-05-07 | Globalwafers Co., Ltd. | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
| JP6344271B2 (ja) * | 2015-03-06 | 2018-06-20 | 信越半導体株式会社 | 貼り合わせ半導体ウェーハ及び貼り合わせ半導体ウェーハの製造方法 |
| US9881832B2 (en) * | 2015-03-17 | 2018-01-30 | Sunedison Semiconductor Limited (Uen201334164H) | Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof |
| FR3037438B1 (fr) * | 2015-06-09 | 2017-06-16 | Soitec Silicon On Insulator | Procede de fabrication d'un element semi-conducteur comprenant une couche de piegeage de charges |
| KR101666753B1 (ko) | 2015-06-18 | 2016-10-14 | 주식회사 동부하이텍 | 고비저항 기판 상에 형성된 반도체 소자 및 무선 주파수 모듈 |
-
2017
- 2017-01-26 FR FR1750646A patent/FR3062238A1/fr not_active Withdrawn
-
2018
- 2018-01-11 EP EP18700172.2A patent/EP3574519B1/fr active Active
- 2018-01-11 KR KR1020197024048A patent/KR20190108138A/ko not_active Application Discontinuation
- 2018-01-11 WO PCT/EP2018/050677 patent/WO2018137937A1/fr unknown
- 2018-01-11 CN CN201880007067.4A patent/CN110199375A/zh active Pending
- 2018-01-11 SG SG11201906017UA patent/SG11201906017UA/en unknown
- 2018-01-11 US US16/476,415 patent/US11373856B2/en active Active
- 2018-01-11 JP JP2019538671A patent/JP2020505769A/ja active Pending
- 2018-01-12 TW TW107101223A patent/TW201841341A/zh unknown
-
2022
- 2022-06-02 US US17/805,206 patent/US20220301847A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US11373856B2 (en) | 2022-06-28 |
| US20220301847A1 (en) | 2022-09-22 |
| JP2020505769A (ja) | 2020-02-20 |
| KR20190108138A (ko) | 2019-09-23 |
| EP3574519B1 (fr) | 2020-08-19 |
| EP3574519A1 (fr) | 2019-12-04 |
| TW201841341A (zh) | 2018-11-16 |
| CN110199375A (zh) | 2019-09-03 |
| US20200020520A1 (en) | 2020-01-16 |
| FR3062238A1 (fr) | 2018-07-27 |
| WO2018137937A1 (fr) | 2018-08-02 |
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