SG11201811065SA - Memory cell imprint avoidance - Google Patents
Memory cell imprint avoidanceInfo
- Publication number
- SG11201811065SA SG11201811065SA SG11201811065SA SG11201811065SA SG11201811065SA SG 11201811065S A SG11201811065S A SG 11201811065SA SG 11201811065S A SG11201811065S A SG 11201811065SA SG 11201811065S A SG11201811065S A SG 11201811065SA SG 11201811065S A SG11201811065S A SG 11201811065SA
- Authority
- SG
- Singapore
- Prior art keywords
- cell
- international
- boise
- idaho
- logic state
- Prior art date
Links
- 230000008520 organization Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2275—Writing or programming circuits or methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2273—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Heterocyclic Carbon Compounds Containing A Hetero Ring Having Oxygen Or Sulfur (AREA)
- Peptides Or Proteins (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/188,886 US9721639B1 (en) | 2016-06-21 | 2016-06-21 | Memory cell imprint avoidance |
| PCT/US2017/035758 WO2017222786A1 (en) | 2016-06-21 | 2017-06-02 | Memory cell imprint avoidance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11201811065SA true SG11201811065SA (en) | 2019-01-30 |
Family
ID=59382659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11201811065SA SG11201811065SA (en) | 2016-06-21 | 2017-06-02 | Memory cell imprint avoidance |
Country Status (8)
| Country | Link |
|---|---|
| US (5) | US9721639B1 (zh) |
| EP (2) | EP3472838B1 (zh) |
| JP (2) | JP7118012B2 (zh) |
| KR (2) | KR102349353B1 (zh) |
| CN (2) | CN112967742A (zh) |
| SG (1) | SG11201811065SA (zh) |
| TW (2) | TWI632548B (zh) |
| WO (1) | WO2017222786A1 (zh) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9697913B1 (en) * | 2016-06-10 | 2017-07-04 | Micron Technology, Inc. | Ferroelectric memory cell recovery |
| US9721639B1 (en) | 2016-06-21 | 2017-08-01 | Micron Technology, Inc. | Memory cell imprint avoidance |
| US10446502B2 (en) | 2017-08-30 | 2019-10-15 | Micron, Technology, Inc. | Apparatuses and methods for shielded memory architecture |
| US10388351B2 (en) | 2017-08-30 | 2019-08-20 | Micron Technology, Inc. | Wear leveling for random access and ferroelectric memory |
| US10431281B1 (en) * | 2018-08-17 | 2019-10-01 | Micron Technology, Inc. | Access schemes for section-based data protection in a memory device |
| US10991411B2 (en) | 2018-08-17 | 2021-04-27 | Micron Technology, Inc. | Method and apparatuses for performing a voltage adjustment operation on a section of memory cells based on a quantity of access operations |
| US10622065B2 (en) * | 2018-09-12 | 2020-04-14 | Micron Technology, Inc. | Dedicated commands for memory operations |
| US11456033B2 (en) | 2018-09-12 | 2022-09-27 | Micron Technology, Inc. | Dedicated commands for memory operations |
| US12081331B2 (en) * | 2018-10-12 | 2024-09-03 | Micron Technology, Inc. | Adapting channel current |
| US10839935B2 (en) * | 2019-02-05 | 2020-11-17 | International Business Machines Corporation | Dynamic redundancy for memory |
| US10692557B1 (en) * | 2019-04-11 | 2020-06-23 | Micron Technology, Inc. | Reference voltage management |
| US11094394B2 (en) | 2019-09-24 | 2021-08-17 | Micron Technology, Inc. | Imprint management for memory |
| US10998080B2 (en) * | 2019-09-24 | 2021-05-04 | Micron Technology, Inc. | Imprint recovery for memory cells |
| US12019506B2 (en) * | 2019-09-24 | 2024-06-25 | Micron Technology, Inc. | Imprint recovery management for memory systems |
| US11244739B2 (en) * | 2019-12-23 | 2022-02-08 | Micron Technology, Inc. | Counter-based read in memory device |
| TWI766462B (zh) | 2019-12-23 | 2022-06-01 | 美商美光科技公司 | 在記憶體裝置中基於計數器之讀取 |
| US11521979B2 (en) * | 2020-12-04 | 2022-12-06 | Micron Technology, Inc. | Power gating in a memory device |
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| JP3191550B2 (ja) | 1994-02-15 | 2001-07-23 | 松下電器産業株式会社 | 半導体メモリ装置 |
| US5525528A (en) * | 1994-02-23 | 1996-06-11 | Ramtron International Corporation | Ferroelectric capacitor renewal method |
| TW378323B (en) * | 1994-09-22 | 2000-01-01 | Matsushita Electric Ind Co Ltd | Ferroelectric memory device |
| JP3919312B2 (ja) * | 1996-12-27 | 2007-05-23 | ローム株式会社 | 強誘電体記憶装置 |
| US6246603B1 (en) | 2000-06-30 | 2001-06-12 | Stmicroelectronics, Inc. | Circuit and method for substantially preventing imprint effects in a ferroelectric memory device |
| JP2002184172A (ja) | 2000-10-04 | 2002-06-28 | Rohm Co Ltd | データ記憶装置 |
| JP2002124100A (ja) * | 2000-10-16 | 2002-04-26 | Matsushita Electric Ind Co Ltd | 強誘電体メモリデバイス |
| JP2002343078A (ja) | 2001-05-21 | 2002-11-29 | Matsushita Electric Ind Co Ltd | 強誘電体メモリ装置 |
| US6522570B1 (en) * | 2001-12-13 | 2003-02-18 | Micron Technology, Inc. | System and method for inhibiting imprinting of capacitor structures of a memory |
| US6650562B2 (en) * | 2002-01-23 | 2003-11-18 | Hewlett-Packard Development Company, L.P. | System and method for determining the logic state of a memory cell in a magnetic tunnel junction memory device |
| US6809949B2 (en) * | 2002-05-06 | 2004-10-26 | Symetrix Corporation | Ferroelectric memory |
| US6590798B1 (en) * | 2002-05-08 | 2003-07-08 | Texas Instruments Incorporated | Apparatus and methods for imprint reduction for ferroelectric memory cell |
| KR100448921B1 (ko) * | 2002-05-21 | 2004-09-16 | 삼성전자주식회사 | 고속 강유전체 메모리 장치 및 그것의 기입 방법 |
| KR100496858B1 (ko) * | 2002-08-02 | 2005-06-22 | 삼성전자주식회사 | 비트라인 클램핑 전압에 상관없이 기준 셀로 일정 전류가흐르는 마그네틱 랜덤 억세스 메모리 |
| US20040190322A1 (en) * | 2003-03-28 | 2004-09-30 | Baumann Robert C | Circuit and method for reducing the effects of memory imprinting |
| US6954373B2 (en) * | 2003-06-27 | 2005-10-11 | Hewlett-Packard Development Company, L.P. | Apparatus and method for determining the logic state of a magnetic tunnel junction memory device |
| JP4270994B2 (ja) * | 2003-09-29 | 2009-06-03 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| US6950328B2 (en) * | 2003-12-11 | 2005-09-27 | Infineon Technologies Ag | Imprint suppression circuit scheme |
| NO322040B1 (no) * | 2004-04-15 | 2006-08-07 | Thin Film Electronics Asa | Bimodal drift av ferroelektriske og elektrete minneceller og innretninger |
| JP4117683B2 (ja) * | 2004-07-20 | 2008-07-16 | セイコーエプソン株式会社 | 強誘電体メモリ装置及びその駆動方法 |
| KR100665841B1 (ko) * | 2004-12-14 | 2007-01-09 | 삼성전자주식회사 | 강유전체 메모리장치의 구동회로 |
| KR100665844B1 (ko) * | 2005-01-04 | 2007-01-09 | 삼성전자주식회사 | 강유전체 메모리 장치 및 그의 구동방법 |
| JP2008527584A (ja) * | 2005-01-04 | 2008-07-24 | シン フイルム エレクトロニクス エイエスエイ | 受動マトリクス・アドレッシング方式の強誘電体又はエレクトレット・メモリ・デバイスの動作方法 |
| KR100702840B1 (ko) * | 2005-07-13 | 2007-04-03 | 삼성전자주식회사 | 강유전체 메모리 장치 및 그에 따른 라이팅 구간 제어방법 |
| JP2008071440A (ja) * | 2006-09-14 | 2008-03-27 | Matsushita Electric Ind Co Ltd | 強誘電体メモリ装置及びその制御方法 |
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| US7729156B2 (en) * | 2007-12-26 | 2010-06-01 | Texas Instruments Incorporated | Cycling to mitigate imprint in ferroelectric memories |
| US8495438B2 (en) * | 2007-12-28 | 2013-07-23 | Texas Instruments Incorporated | Technique for memory imprint reliability improvement |
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| KR101497545B1 (ko) * | 2008-09-12 | 2015-03-03 | 삼성전자주식회사 | 프리 페이지 검출 방법 및 장치와 이를 이용한 에러 정정 코드 디코딩 방법 및 장치 |
| JP5185098B2 (ja) * | 2008-12-22 | 2013-04-17 | 株式会社東芝 | 強誘電体メモリ |
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| CN104067247A (zh) * | 2012-01-16 | 2014-09-24 | 索尼公司 | 存储控制装置，存储装置，信息处理系统及其处理方法 |
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| KR102140784B1 (ko) * | 2013-12-03 | 2020-08-03 | 삼성전자주식회사 | 비휘발성 메모리 장치의 데이터 기록 방법 |
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| JP6444668B2 (ja) * | 2014-09-10 | 2018-12-26 | ローム株式会社 | データ保持制御回路、データ書込方法、データ読出方法、強誘電体記憶部の特性テスト方法、半導体チップ |
| US9721639B1 (en) * | 2016-06-21 | 2017-08-01 | Micron Technology, Inc. | Memory cell imprint avoidance |
-
2016
- 2016-06-21 US US15/188,886 patent/US9721639B1/en active Active
-
2017
- 2017-06-02 KR KR1020217005080A patent/KR102349353B1/ko active IP Right Grant
- 2017-06-02 KR KR1020197001496A patent/KR102220990B1/ko active IP Right Grant
- 2017-06-02 JP JP2018566450A patent/JP7118012B2/ja active Active
- 2017-06-02 CN CN202110295522.9A patent/CN112967742A/zh active Pending
- 2017-06-02 EP EP17815913.3A patent/EP3472838B1/en active Active
- 2017-06-02 EP EP21189181.7A patent/EP3926629A1/en active Pending
- 2017-06-02 WO PCT/US2017/035758 patent/WO2017222786A1/en unknown
- 2017-06-02 CN CN201780038707.3A patent/CN109313921B/zh active Active
- 2017-06-02 SG SG11201811065SA patent/SG11201811065SA/en unknown
- 2017-06-20 TW TW106120565A patent/TWI632548B/zh active
- 2017-06-20 TW TW107122763A patent/TWI663596B/zh active
- 2017-07-10 US US15/645,106 patent/US10083732B2/en active Active
-
2018
- 2018-08-23 US US16/111,021 patent/US10475500B2/en active Active
-
2019
- 2019-09-27 US US16/586,334 patent/US10978128B2/en active Active
-
2021
- 2021-03-24 US US17/211,246 patent/US11501817B2/en active Active
- 2021-06-24 JP JP2021105039A patent/JP2021166114A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| TWI632548B (zh) | 2018-08-11 |
| EP3472838A1 (en) | 2019-04-24 |
| CN109313921A (zh) | 2019-02-05 |
| US10475500B2 (en) | 2019-11-12 |
| TW201907398A (zh) | 2019-02-16 |
| US11501817B2 (en) | 2022-11-15 |
| KR102349353B1 (ko) | 2022-01-10 |
| US9721639B1 (en) | 2017-08-01 |
| EP3472838A4 (en) | 2020-03-04 |
| TWI663596B (zh) | 2019-06-21 |
| EP3926629A1 (en) | 2021-12-22 |
| KR20210022158A (ko) | 2021-03-02 |
| JP7118012B2 (ja) | 2022-08-15 |
| JP2021166114A (ja) | 2021-10-14 |
| KR20190017999A (ko) | 2019-02-20 |
| CN112967742A (zh) | 2021-06-15 |
| KR102220990B1 (ko) | 2021-03-02 |
| US20210280231A1 (en) | 2021-09-09 |
| US20200090728A1 (en) | 2020-03-19 |
| TW201802807A (zh) | 2018-01-16 |
| US10083732B2 (en) | 2018-09-25 |
| US20180366176A1 (en) | 2018-12-20 |
| US20170365323A1 (en) | 2017-12-21 |
| JP2019525375A (ja) | 2019-09-05 |
| US10978128B2 (en) | 2021-04-13 |
| EP3472838B1 (en) | 2021-08-04 |
| CN109313921B (zh) | 2021-04-02 |
| WO2017222786A1 (en) | 2017-12-28 |
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