SG10201403206VA - Semiconductor device and method of forming low profile 3d fan-out package - Google Patents

Semiconductor device and method of forming low profile 3d fan-out package

Info

Publication number
SG10201403206VA
SG10201403206VA SG10201403206VA SG10201403206VA SG10201403206VA SG 10201403206V A SG10201403206V A SG 10201403206VA SG 10201403206V A SG10201403206V A SG 10201403206VA SG 10201403206V A SG10201403206V A SG 10201403206VA SG 10201403206V A SG10201403206V A SG 10201403206VA
Authority
SG
Singapore
Prior art keywords
substrate
encapsulant
conductive layer
opening
semiconductor die
Prior art date
Application number
SG10201403206VA
Other languages
English (en)
Inventor
Yaojian Lin
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of SG10201403206VA publication Critical patent/SG10201403206VA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1082—Shape of the containers for improving alignment between containers, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1088—Arrangements to limit the height of the assembly
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
SG10201403206VA 2013-06-28 2014-06-12 Semiconductor device and method of forming low profile 3d fan-out package SG10201403206VA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/931,397 US8980691B2 (en) 2013-06-28 2013-06-28 Semiconductor device and method of forming low profile 3D fan-out package

Publications (1)

Publication Number Publication Date
SG10201403206VA true SG10201403206VA (en) 2015-01-29

Family

ID=52114800

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201403206VA SG10201403206VA (en) 2013-06-28 2014-06-12 Semiconductor device and method of forming low profile 3d fan-out package

Country Status (4)

Country Link
US (1) US8980691B2 (zh)
CN (1) CN104253105B (zh)
SG (1) SG10201403206VA (zh)
TW (1) TWI541915B (zh)

Families Citing this family (104)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9842798B2 (en) 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US10049964B2 (en) * 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US9899133B2 (en) 2013-08-01 2018-02-20 Qorvo Us, Inc. Advanced 3D inductor structures with confined magnetic field
US9294045B2 (en) 2013-03-15 2016-03-22 Rf Micro Devices, Inc. Gain and phase calibration for closed loop feedback linearized amplifiers
US9705478B2 (en) 2013-08-01 2017-07-11 Qorvo Us, Inc. Weakly coupled tunable RF receiver architecture
KR20140126598A (ko) * 2013-04-23 2014-10-31 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9691745B2 (en) 2013-06-26 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structure for forming a package on package (PoP) structure and method for forming the same
US9252076B2 (en) * 2013-08-07 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9093337B2 (en) 2013-09-27 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for controlling warpage in packaging
US9735082B2 (en) * 2013-12-04 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC packaging with hot spot thermal management features
TWI556402B (zh) * 2014-01-02 2016-11-01 矽品精密工業股份有限公司 封裝堆疊結構及其製法
US9406650B2 (en) 2014-01-31 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and packaged semiconductor devices
US20150287697A1 (en) 2014-04-02 2015-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
US9252135B2 (en) 2014-02-13 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
FR3018953B1 (fr) 2014-03-19 2017-09-15 St Microelectronics Crolles 2 Sas Puce de circuit integre montee sur un interposeur
US9431335B2 (en) * 2014-10-24 2016-08-30 Dyi-chung Hu Molding compound supported RDL for IC package
US9754849B2 (en) * 2014-12-23 2017-09-05 Intel Corporation Organic-inorganic hybrid structure for integrated circuit packages
CN105990288B (zh) 2015-01-30 2019-03-12 日月光半导体制造股份有限公司 半导体衬底及其制造方法
US9786623B2 (en) 2015-03-17 2017-10-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming PoP semiconductor device with RDL over top package
US9602804B2 (en) * 2015-03-26 2017-03-21 Intel Corporation Methods of forming integrated package structures with low Z height 3D camera
US10199337B2 (en) * 2015-05-11 2019-02-05 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
US9984979B2 (en) 2015-05-11 2018-05-29 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package and method of manufacturing the same
US9837484B2 (en) * 2015-05-27 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming substrate including embedded component with symmetrical structure
US11018025B2 (en) 2015-07-31 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution lines having stacking vias
US10796835B2 (en) * 2015-08-24 2020-10-06 Qorvo Us, Inc. Stacked laminate inductors for high module volume utilization and performance-cost-size-processing-time tradeoff
US20170081178A1 (en) * 2015-09-22 2017-03-23 Freescale Semiconductor, Inc. Semiconductor device package with seal structure
US9646853B1 (en) * 2015-10-15 2017-05-09 Freescale Semiconductor, Inc. IC device having patterned, non-conductive substrate
KR101933408B1 (ko) * 2015-11-10 2018-12-28 삼성전기 주식회사 전자부품 패키지 및 이를 포함하는 전자기기
US9711458B2 (en) 2015-11-13 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method for chip package
KR101681031B1 (ko) * 2015-11-17 2016-12-01 주식회사 네패스 반도체 패키지 및 그 제조방법
KR20170067426A (ko) * 2015-12-08 2017-06-16 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 제조 방법 및 이를 이용한 반도체 패키지
US10165682B2 (en) 2015-12-28 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Opening in the pad for bonding integrated passive device in InFO package
KR102015335B1 (ko) 2016-03-15 2019-08-28 삼성전자주식회사 전자부품 패키지 및 그 제조방법
US9659911B1 (en) * 2016-04-20 2017-05-23 Powertech Technology Inc. Package structure and manufacturing method thereof
US10600748B2 (en) 2016-06-20 2020-03-24 Samsung Electronics Co., Ltd. Fan-out semiconductor package
US20170365567A1 (en) * 2016-06-20 2017-12-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
KR101952863B1 (ko) * 2016-06-21 2019-02-28 삼성전기주식회사 팬-아웃 반도체 패키지
JP6562467B2 (ja) 2016-06-21 2019-08-21 サムスン エレクトロニクス カンパニー リミテッド ファン−アウト半導体パッケージ
KR101994752B1 (ko) * 2016-07-26 2019-07-01 삼성전기주식회사 팬-아웃 반도체 패키지
US9853003B1 (en) * 2016-07-26 2017-12-26 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
KR102016491B1 (ko) * 2016-10-10 2019-09-02 삼성전기주식회사 팬-아웃 반도체 패키지
US10600679B2 (en) 2016-11-17 2020-03-24 Samsung Electronics Co., Ltd. Fan-out semiconductor package
KR101872619B1 (ko) * 2016-11-17 2018-06-28 삼성전기주식회사 팬-아웃 반도체 패키지
US10381300B2 (en) * 2016-11-28 2019-08-13 Advanced Semiconductor Engineering, Inc. Semiconductor device package including filling mold via
US11139238B2 (en) 2016-12-07 2021-10-05 Qorvo Us, Inc. High Q factor inductor structure
KR101983186B1 (ko) 2016-12-16 2019-05-28 삼성전기주식회사 팬-아웃 반도체 패키지
US10784220B2 (en) 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
TWI614844B (zh) * 2017-03-31 2018-02-11 矽品精密工業股份有限公司 封裝堆疊結構及其製法
US10510709B2 (en) * 2017-04-20 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor package and manufacturing method thereof
US20180315672A1 (en) * 2017-04-26 2018-11-01 Qualcomm Incorporated Sacrificial test pads for inline test access
US10867924B2 (en) 2017-07-06 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing
US10157864B1 (en) * 2017-07-27 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming the same
US10541153B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10804115B2 (en) * 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US11024569B2 (en) * 2017-08-09 2021-06-01 Advanced Semiconducor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10157870B1 (en) * 2017-09-26 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10886263B2 (en) * 2017-09-29 2021-01-05 Advanced Semiconductor Engineering, Inc. Stacked semiconductor package assemblies including double sided redistribution layers
TWI626460B (zh) 2017-10-25 2018-06-11 財團法人工業技術研究院 凸塊良率預判及重配置方法及電腦可讀取儲存媒體
KR101963292B1 (ko) 2017-10-31 2019-03-28 삼성전기주식회사 팬-아웃 반도체 패키지
KR102019355B1 (ko) * 2017-11-01 2019-09-09 삼성전자주식회사 반도체 패키지
US20190164948A1 (en) * 2017-11-27 2019-05-30 Powertech Technology Inc. Package structure and manufacturing method thereof
US10163693B1 (en) 2017-12-21 2018-12-25 Micron Technology, Inc. Methods for processing semiconductor dice and fabricating assemblies incorporating same
US10468339B2 (en) * 2018-01-19 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous fan-out structure and method of manufacture
JP7046639B2 (ja) * 2018-02-21 2022-04-04 新光電気工業株式会社 配線基板及びその製造方法
KR102086364B1 (ko) * 2018-03-05 2020-03-09 삼성전자주식회사 반도체 패키지
KR102071457B1 (ko) * 2018-03-13 2020-01-30 삼성전자주식회사 팬-아웃 반도체 패키지
US10573573B2 (en) * 2018-03-20 2020-02-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package and package-on-package structure having elliptical conductive columns
US10510595B2 (en) 2018-04-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US11075151B2 (en) * 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package with controllable standoff
CN110797293A (zh) * 2018-08-01 2020-02-14 矽品精密工业股份有限公司 封装堆叠结构及其制法暨封装结构
KR102551034B1 (ko) * 2018-09-07 2023-07-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
US10790162B2 (en) * 2018-09-27 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
KR20200051215A (ko) * 2018-11-05 2020-05-13 삼성전기주식회사 인쇄회로기판 및 이를 포함하는 패키지 구조물
KR102530319B1 (ko) 2018-12-07 2023-05-09 삼성전자주식회사 전도성 필라를 갖는 반도체 패키지 및 그 제조 방법
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
US11081369B2 (en) * 2019-02-25 2021-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof
IT201900006740A1 (it) * 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
US10998231B2 (en) * 2019-06-13 2021-05-04 Nxp Usa, Inc. Method for increasing semiconductor device wafer strength
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US11387373B2 (en) * 2019-07-29 2022-07-12 Nxp Usa, Inc. Low drain-source on resistance semiconductor component and method of fabrication
US11682600B2 (en) * 2019-08-07 2023-06-20 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Protection layer for panel handling systems
TWI707410B (zh) 2019-08-07 2020-10-11 久元電子股份有限公司 具散熱功能的晶片封裝模組及其製造方法
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
DE102019219238A1 (de) * 2019-12-10 2021-06-10 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Mehrlagiges 3D-Folienpackage
CN113013130A (zh) * 2019-12-20 2021-06-22 奥特斯科技(重庆)有限公司 具有双介电层的部件承载件及其制造方法
KR20210105255A (ko) * 2020-02-18 2021-08-26 삼성전자주식회사 반도체 패키지, 및 이를 가지는 패키지 온 패키지
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
KR20210115160A (ko) * 2020-03-12 2021-09-27 삼성전자주식회사 Pid를 포함하는 반도체 패키지 및 이의 제조 방법
KR20210126228A (ko) 2020-04-10 2021-10-20 삼성전자주식회사 반도체 패키지
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
JP2022088990A (ja) * 2020-12-03 2022-06-15 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
KR20220109753A (ko) * 2021-01-29 2022-08-05 삼성전자주식회사 포스트를 포함하는 반도체 패키지
US11854927B2 (en) 2021-03-24 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of forming same
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
US20230178508A1 (en) * 2021-12-08 2023-06-08 Nxp Usa, Inc. Semiconductor device with open cavity and method therefor
US20230268304A1 (en) * 2022-02-23 2023-08-24 Nxp Usa, Inc. Semiconductor device with open cavity and method therefor

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077301A (ja) * 1999-08-24 2001-03-23 Amkor Technology Korea Inc 半導体パッケージ及びその製造方法
SG108245A1 (en) * 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
US6790710B2 (en) * 2002-01-31 2004-09-14 Asat Limited Method of manufacturing an integrated circuit package
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
KR100792352B1 (ko) * 2006-07-06 2008-01-08 삼성전기주식회사 패키지 온 패키지의 바텀기판 및 그 제조방법
KR100849210B1 (ko) * 2006-12-22 2008-07-31 삼성전자주식회사 플러그 앤 소켓 형상의 와이어 연결을 갖도록 형성된적층형 반도체 패키지
KR100811034B1 (ko) * 2007-04-30 2008-03-06 삼성전기주식회사 전자소자 내장 인쇄회로기판의 제조방법
KR101194842B1 (ko) * 2007-09-06 2012-10-25 삼성전자주식회사 반도체 패키지가 삽입된 인쇄회로기판
JP5395360B2 (ja) * 2008-02-25 2014-01-22 新光電気工業株式会社 電子部品内蔵基板の製造方法
US8093704B2 (en) * 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
US8258019B2 (en) * 2008-06-30 2012-09-04 Intel Corporation Flip chip assembly process for ultra thin substrate and package on package assembly
TWI473553B (zh) * 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US20110024899A1 (en) * 2009-07-28 2011-02-03 Kenji Masumoto Substrate structure for cavity package
US8884422B2 (en) 2009-12-31 2014-11-11 Stmicroelectronics Pte Ltd. Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8304878B2 (en) * 2010-05-17 2012-11-06 Advanced Semiconductor Engineering, Inc. Embedded component substrate, semiconductor package structure using the same and fabrication methods thereof
US20120126399A1 (en) * 2010-11-22 2012-05-24 Bridge Semiconductor Corporation Thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
US8848380B2 (en) * 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction

Also Published As

Publication number Publication date
CN104253105B (zh) 2017-05-17
US20150001708A1 (en) 2015-01-01
TW201501223A (zh) 2015-01-01
TWI541915B (zh) 2016-07-11
US8980691B2 (en) 2015-03-17
CN104253105A (zh) 2014-12-31

Similar Documents

Publication Publication Date Title
SG10201403206VA (en) Semiconductor device and method of forming low profile 3d fan-out package
WO2016209668A3 (en) Structures and methods for reliable packages
SG10201900070UA (en) Semiconductor device and method of forming double-sidedfan-out wafer level package
EP3125283A3 (en) Semiconductor device and method of forming a reduced thickness semiconductor package
SG10201403211QA (en) Semiconductor device and method of stacking semiconductordie on a fan-out wlcsp
GB2548070A (en) Stacked semiconductor device package with improved interconnect bandwidth
EP4220709A3 (en) Ground via clustering for crosstalk mitigation
SG169266A1 (en) Semiconductor device and method of dualmolding die formed on opposite sides of build-up interconnect structure
SG169931A1 (en) Semiconductor device and method of forming open cavity in tsv interposer to contain semiconductor die in wlcsmp
WO2014112954A8 (en) Substrate for semiconductor packaging and method of forming same
GB201020062D0 (en) Multi-chip package
EP3651193A3 (en) Moulded semiconductor package with capacitive and inductive components
SG168468A1 (en) Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path between die
WO2015123426A3 (en) Integrated device comprising stacked dies on redistribution layers
SG170693A1 (en) Semiconductor package and method of mounting semiconductor die to opposite sides of tsv substrate
TW201612927A (en) Circuit protection device and method of manufacturing same
SG169268A1 (en) Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package
SG165232A1 (en) Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors
MY184096A (en) Method and apparatus for forming backside die planar devices and saw filter
EP2779237A3 (en) A chip arrangement and a method for manufacturing a chip arrangement
SG10201809052TA (en) Semiconductor device and method offorming flipchip interconnect structure
SG165231A1 (en) Semiconductor die and method of forming noise absorbing regions between thvs in peripheral region of the die
GB2523500A (en) Landing structure for through-silicon via
WO2011088384A3 (en) Solder pillars in flip chip assembly and manufacturing method thereof
WO2012140050A3 (de) Verfahren zur herstellung eines licht emittierenden halbleiterbauelements und licht emittierendes halbleiterbauelement