TWI707410B - 具散熱功能的晶片封裝模組及其製造方法 - Google Patents
具散熱功能的晶片封裝模組及其製造方法 Download PDFInfo
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- TWI707410B TWI707410B TW108128151A TW108128151A TWI707410B TW I707410 B TWI707410 B TW I707410B TW 108128151 A TW108128151 A TW 108128151A TW 108128151 A TW108128151 A TW 108128151A TW I707410 B TWI707410 B TW I707410B
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- chip
- layer
- circuit board
- heat dissipation
- dielectric layer
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Abstract
本發明公開一種具散熱功能的晶片封裝模組及其製造方法。晶片封裝模組的製造方法包括:提供具有對位圖案的暫時性承載板,其包括底板以及設置於底板上的可剝離黏著材料;根據對位圖案,將線路板設置於暫時性承載板上,且線路板具有貫穿線路板的晶片容置空間;根據對位圖案,將晶片以主動面朝向暫時性承載板而設置於晶片容置空間內,且晶片通過可剝離黏著材料固定於暫時性承載板上;形成膠材於晶片容置空間內,以使晶片連接並固定於線路板,而形成一初始封裝體;分離初始封裝體以及暫時性承載板;以及在初始封裝體的底側形成一導電散熱層直接接觸並覆蓋晶片的底面。
Description
本發明涉及一種晶片封裝模組及其製造方法,特別是涉及一種具有散熱功能的晶片封裝模組及其製造方法。
功率元件可應用於電能轉換電路或是控制電路中,是電子產品中進行功率處理的核心元件。隨著電子產品朝向輕量化的發展趨勢,應用於電子產品中的功率元件封裝結構也朝向薄型化、高功率以及高密度發展。
由於功率元件通常會在高電流或高電壓的條件下操作,因此,功率元件所產生的熱能會使溫度升高。若是無法適時對功率元件散熱,功率元件可能會因為溫度過高而無法正常運作。另一方面,功率元件若經常處於過高的溫度下操作,也會縮短功率元件的壽命。
在美國專利號US6506632中,揭露一種積體電路封裝(integrated circuit package)的方法。在該專利案中,先將一核心層(core layer)與一導電層相互貼合,且導電層貼合於核心層的第二表面,以提供一基板。接著,在基板中形成第一開口,以裸露出一部分導電層。之後,晶片以背面朝向導電層,並被貼附在被裸露的導電層上,且晶片的正面具有多個接墊。將介電層填入第一開口內,並覆蓋晶片的正面以及多個接墊。之後,形成用以電性連接於晶片的接墊的多個通孔、圖案化金屬層以及多個焊球(solder balls)。
然而,在上述製造方法中,晶片可能並未直接與導電層接觸,而是通過膠層固定在導電層上。由於膠層的導熱較差,會導致晶片的散熱效果不理想。另外,在形成第一開口以裸露出一部分導電層的步驟中,會使導電層的表面不平整,若晶片並未通過膠層固定於導電層上,導電層的表面也很難貼合晶片的底面。
另一方面,當晶片被設置在第一開口內時,對位精準度較差。此外,在將介電層填入第一開口內時,也可能會使晶片位移或者旋轉一角度。由於後續所形成多個通孔以及圖案化金屬層的位置是對應於晶片的預設位置,若晶片因對位不精準或是在填入介電層時偏移預設位置,多個通孔以及圖案化金屬層會與晶片相互錯位,而導致圖案化金屬層與晶片之間無法建立電性連接或是造成短路。特別是當晶片上的焊墊數量較多或者排列較密集時,對位不精準所造成的問題會更嚴重。
本發明所要解決的技術問題在於,如何避免晶片在封裝製程中,因對位不精準而造成良率降低,以及提升晶片的散熱效果,以避免晶片因溫度過高而無法正常運作或導致晶片壽命縮短。
為了解決上述的技術問題,本發明所採用的其中一技術方案是,提供一種具散熱功能的晶片封裝模組的製造方法,其包括:提供一具有一對位圖案的暫時性承載板,暫時性承載板包括一底板以及設置於底板上的一可剝離黏著材料;根據對位圖案,將一線路板設置於暫時性承載板上,其中,線路板具有貫穿線路板的一晶片容置空間;根據對位圖案,將一晶片以主動面朝向暫時性承載板而設置於晶片容置空間內,其中,晶片通過可剝離黏著材料固定於暫時性承載板上;填入一膠材於晶片容置空間內,以使晶片
連接並固定於線路板,而形成一初始封裝體;分離初始封裝體以及暫時性承載板,其中,晶片的底面裸露於初始封裝體的底側;以及在初始封裝體的底側形成一導電散熱層直接接觸並覆蓋晶片的底面。
提供一種具散熱功能的晶片封裝模組,其包括線路板、晶片、膠材以及導電散熱層。線路板具有第一表面以及與第一表面相反的第二表面,且線路板具有一晶片容置空間,晶片容置空間由線路板的第一表面延伸至第二表面。晶片設置在晶片容置空間內,並具有主動面以及與主動面相反的底面。膠材填充於晶片的側表面與晶片容置空間的側壁之間,以使晶片固定於線路板。導電散熱層設置並接觸於晶片的底面。
本發明的其中一有益效果在於,本發明所提供的具散熱功能的晶片封裝模組及其製造方法,其能通過“提供一具有一對位圖案的暫時性承載板”,“根據對位圖案,將一線路板設置於暫時性承載板上”以及“根據對位圖案,將一晶片以主動面朝向暫時性承載板而設置於晶片容置空間內”的技術手段,可以使線路板與晶片之間的對位更精準。另外,本發明所提供的具散熱功能的晶片封裝模組中,通過“導電散熱層設置並接觸於晶片的底面”的技術方案,可提升導電散熱層對晶片的散熱效果。
為使能更進一步瞭解本發明的特徵及技術內容,請參閱以下有關本發明的詳細說明與圖式,然而所提供的圖式僅用於提供參考與說明,並非用來對本發明加以限制。
P:暫時性承載板
P1:底板
P2:可剝離黏著材料
P10:對位圖案
P11:線路板對位標記
P12:晶片對位標記
M1:晶片封裝模組
M1’:初始封裝體
10:線路板
10a:第一表面
10b:第二表面
100:核心基板
100S:晶片容置空間
100h:導電通孔
101:第一導線層
102:第二導線層
103:第一介電層
103p:第一開口圖案
104:第二介電層
104p:第二開口圖案
20:晶片
20a:主動面
20b:底面
20s:側表面
200:焊墊
30:膠材
30a:頂表面
30b:底表面
40:導電散熱層
50:上層重分布線路結構
500:第一上介電層
501a、501b:導電柱
502:內連線路層
503:第二上介電層
504:上方金屬焊墊
60:下層重分布線路結構
600:下介電層
600a:散熱開口
600b:焊墊開口
601:下方金屬焊墊
圖1為本發明實施例的具散熱功能的晶片封裝模組的製造方法的流程圖。
圖2A為本發明實施例的暫時性承載板的剖面示意圖。
圖2B為本發明實施例的暫時性承載板的俯視示意圖。
圖3至圖4為本發明實施例的晶片封裝模組在製造方法中的步驟S110的剖面示意圖。
圖5為本發明實施例的晶片封裝模組在製造方法中的步驟S120剖面示意圖。
圖6為本發明實施例的晶片封裝模組在製造方法中的步驟S130剖面示意圖。
圖7為本發明實施例的晶片封裝模組在製造方法中的步驟S140剖面示意圖。
圖8至圖9為本發明實施例的晶片封裝模組在製造方法中的步驟S150剖面示意圖。
圖10為本發明實施例的具散熱功能的晶片封裝模組的剖面示意圖。
以下是通過特定的具體實施例來說明本發明所公開有關“具散熱功能的晶片封裝模組及其製造方法”的實施方式,本領域技術人員可由本說明書所公開的內容瞭解本發明的優點與效果。本發明可通過其他不同的具體實施例加以施行或應用,本說明書中的各項細節也可基於不同觀點與應用,在不悖離本發明的構思下進行各種修改與變更。另外,本發明的附圖僅為簡單示意說明,並非依實際尺寸的描繪,事先聲明。以下的實施方式將進一步詳細說明本發明的相關技術內容,但所公開的內容並非用以限制本發明的保護範圍。
應當可以理解的是,雖然本文中可能會使用到“第一”、“第
二”、“第三”等術語來描述各種元件,但這些元件不應受這些術語的限制。這些術語主要是用以區分一元件與另一元件。另外,本文中所使用的術語“或”,應視實際情況可能包括相關聯的列出項目中的任一個或者多個的組合。
參閱圖1,其顯示本發明實施例的具散熱功能的晶片封裝模組的製造方法的流程圖。本發明實施例的製造方法可用以封裝不同種類的晶片,如:功率晶片。
如圖1所示,在步驟S100中,提供一暫時性承載板。暫時性承載板包括一具有對位圖案的底板以及設置於底板上的一可剝離黏著材料。在步驟S110中,根據對位圖案,將一線路板設置於暫時性承載板上,其中,線路板具有貫穿線路板的一晶片容置空間。
在步驟S120中,根據對位圖案,將晶片以主動面朝向暫時性承載板而設置於晶片容置空間內,其中,晶片通過可剝離黏著材料固定於暫時性承載板上。之後,在步驟S130中,填入一膠材於晶片容置空間內,以使晶片連接並固定於線路板,而形成一初始封裝體。
在步驟S140中,分離初始封裝體以及暫時性承載板。之後,在步驟S150中,在初始封裝體的底側形成一導電散熱層直接接觸並覆蓋晶片的底面,以及分別在初始封裝體的底側與頂側形成一下層重分布線路結構以及一上層重分布線路結構。
以下將進一步說明,本發明實施例中,具散熱功能的晶片封裝模組的製造方法的詳細流程。請配合參照圖1中的步驟S100、圖2A以及圖2B。
暫時性承載板P包括一底板P1以及設置於底板P1上的一可剝離黏著材料P2。在本發明實施例中,底板P1的材料可為矽晶圓、玻璃、陶瓷、高分子材料或者金屬材料,且對位圖案P10是形成於底板P1上。
對位圖案P10包括至少一線路板對位標記P11(圖中繪示兩個
為例)以及至少一晶片對位標記P12(圖中繪示兩個為例)。在本發明中,線路板對位標記P11以及晶片對位標記P12的數量並不限制。另外,在本實施例中,可剝離黏著材料P2為一透明材料,以避免遮蓋底板P1上的對位圖案P10。
請配合參照圖1的步驟S110、圖3以及圖4。線路板10具有一第一表面10a以及與第一表面10a相反的第二表面10b。在本實施例中,線路板10具有預先形成的內連線路以及貫穿線路板10的晶片容置空間100S。
具體而言,如圖3所示,線路板10為具有多層結構的複合板,且至少包括核心基板100、第一導線層101、第二導線層102、第一介電層103以及第二介電層104。
核心基板100的材料可以是高分子、塑膠、陶瓷、金屬、矽晶圓、複合材料(如:玻璃纖維FR4或BT樹脂)、玻璃或是可撓曲的軟性材料,本發明並不限制。在本實施例中,核心基板100並具有至少一貫穿核心基板100的導電通孔100h(圖1繪示兩個為例)。
第一導線層101與第二導線層102分別設置於核心基板100的兩相反側,並通過導電通孔100h而彼此電性連接。進一步而言,第一導線層101與第二導線層102可通過微影蝕刻而形成,並可分別具有不同的線路圖案。
第一導線層101以及第二導線層102的材料可以是金屬、合金或者複合導電材料。金屬或合金例如是由銅、銀、鎳、金、錫或其任意組合所組成的群組中的其中一種。在一實施例中,第一導線層101以及第二導線層102的材料例如是銅/鎳/金、銅/鎳/錫。另外,複合導電材料例如是銀膠或碳膠。
第一介電層103與第二介電層104分別設置在核心基板100的兩相反側。在本實施例中,第一介電層103與第二介電層104分別是線路板10的最外側兩層。也就是說,線路板10的第一表面10a包括第一介電層103的外表面,而線路板10的第二表面10b包括第二介電層104的外表面。
進一步而言,第一介電層103設置在第一導線層101上,並具有第一開口圖案103p,以裸露一部分第一導線層101。另外,第二介電層104設置在第二導線層102上,並具有一第二開口圖案104p,以裸露一部分第二導線層102。
第一介電層103與第二介電層104的材料例如是聚醯亞胺(Polyimide,PI)、苯丙環丁烯(Benzocyclobutene,BCB)、矽膠、樹脂、防焊材料(solder mask)、複合材料等絕緣黏著材料。
另外,如圖3所示,晶片容置空間100S由線路板10的第一表面10a延伸至第二表面10b。據此,在本發明實施例中,核心基板100的一部分、第一介電層103的一部分以及第二介電層104的一部分會裸露在晶片容置空間100S的側壁(未標號)。在另一實施例中,第一導線層101的一部分或者第二導線層102的一部分也會裸露於晶片容置空間100S的側壁。
如圖3以及4所示,在設置線路板10於暫時性承載板P上時,線路板10是對應於至少一線路板對位標記P11而設置於暫時性承載板P上。線路板10通過可剝離黏著材料P2而固定於暫時性承載板P上,且晶片對位標記P12會由晶片容置空間100S而被裸露出來。也就是說,在設置線路板10於暫時性承載板P上之後,晶片對位標記P12並不會被線路板10所遮蓋。
請一併參照圖1的步驟S120以及圖5。接著,將晶片20設置於晶片容置空間100S內。晶片20通過可剝離黏著材料P2固定於暫時性承載板P上。
如圖5所示,晶片20具有一主動面20a以及與主動面20a相反的底面20b。另外,晶片20具有位於主動面20a上的至少一焊墊200(圖5繪示兩個為例)。在本發明實施例中,晶片20的主動面20a與第二導線層102都面向相同方向設置。亦即,晶片20的焊墊200與第二導線層102都是位於核心基板100的相
同側。
在將晶片20設置於晶片容置空間100S內的步驟中,主動面20a上的焊墊200對準於對應的晶片對位標記P12而設置於暫時性承載板P上。值得注意的是,在本實施例中,當晶片20設置於晶片容置空間100S內時,所述焊墊200的一部分埋入可剝離黏著材料P2內。
另外,如圖5所示,晶片容置空間100S的大小會略大於晶片20的尺寸,因此晶片容置空間100S的側壁與晶片20的側表面20s之間會定義出一空隙(未標號)。
在本發明實施例中,晶片20的厚度會大致與線路板10的厚度大致相同。據此,晶片20的厚度會大於線路板10的核心基板100的厚度。
請一併參照圖1的步驟S130以及圖6。膠材30被填充於晶片容置空間100S內。進一步而言,膠材30會填充於晶片20的側表面20s以及晶片容置空間100S的一側壁之間,以使晶片20連接並固定於線路板10,而形成一初始封裝體M1’。
膠材30的材料可以是高分子材料,如:聚醯亞胺(Polyimide,PI)、苯丙環丁烯(Benzocyclobutene,BCB),或是矽膠、樹脂、複合材料等具有黏著性的絕緣材料或介電材料,以使晶片20可被固定於線路板10內。
在本發明實施例中,膠材30會包覆晶片20的側表面20s,且膠材30的頂表面30a與線路板10的第二表面10b共平面。另外,膠材30不會完全覆蓋晶片20的底面20b。也就是說,晶片20的至少一部分底面20b會被裸露在初始封裝體M1’的外表面上。
在一實施例中,當晶片20的厚度小於線路板10時,在填充膠材30時,膠材30可能會完全覆蓋晶片20的底面20b。因此,本發明實施例的製造方法還可進一步包括對膠材30執行一清除步驟,以去除覆蓋在晶片20的背面
20b上的一部分膠材30,而使晶片20的底面20b至少一部分(如:中間區域)被裸露出來。
須說明的是,在不同的製程條件或製程限制下,膠材30也可能會局部地覆蓋晶片20的底面20b的周邊區域。因此,只要晶片的底面20b的中間區域不會被膠材30所覆蓋,本發明並沒有限定晶片20的底面20b的膠材30要被完全去除。
另外,值得注意的是,在本發明實施例中,由於晶片20的主動面20a上的焊墊200埋入可剝離黏著材料P2內,因此在填入膠材30時,膠材30不會覆蓋焊墊200。
請一併參照圖1的步驟S140、圖7以及圖8。將初始封裝體M1’以及暫時性承載板P彼此分離。由於可剝離黏著材料P2與底板P1之間的結合力,大於可剝離黏著材料P2與初始封裝體M1’之間的結合力,因此可通過施加外力將初始封裝體M1’以及暫時性承載板P分離,而不會損壞初始封裝體M1’。
另外,如圖8所示,晶片20的主動面20a以及底面20b分別裸露於初始封裝體M1’的頂側與底側。另外,如前所述,位於晶片20的主動面20a上的焊墊200也會被裸露出來。
接著,請參照圖1的步驟S150、圖9以及圖10。在初始封裝體M1’的底側形成一導電散熱層40直接接觸並覆蓋晶片20的底面20b,以及分別在初始封裝體M1’的頂側與底側形成一上層重分布線路結構50以及一下層重分布線路結構60。
在本實施例中,先形成上層重分布線路結構50之後,再形成導電散熱層40以及下層重分布線路結構60。然而,在本發明中,形成導電散熱層40、上層重分布線路結構50以及下層重分布線路結構60的先後順序並
沒有限制。
如圖9所示,上層重分布線路結構50設置於線路板10的第二表面10b上,並電性連接於晶片20。換句話說,晶片20可以通過上層重分布線路結構50以及線路板10,而電性連接於外部電路。
本實施例中,形成上層重分布線路結構50的步驟包括形成第一上介電層500、多個導電柱501a、501b、內連線路層502、第二上介電層503以及上方金屬焊墊504。
具體而言,形成第一上介電層500覆蓋晶片20的主動面20a以及線路板10的第二表面10b(也就是第二介電層104的表面)。第一上介電層500具有多個接觸窗,這些接觸窗分別對應於由第二介電層104的第二開口圖案104p中所裸露的第二導線層102,以及對應於晶片20的焊墊200。
接著,形成至少一導電柱501a設置於第一上介電層500的接觸窗內,以電性連接於晶片20的焊墊200,以及形成另一導電柱501b通過第一上介電層500的接觸窗以及第二介電層104的第二開口圖案104p,而電性連接於第二導線層102。之後,形成內連線路層502設置於第一上介電層500上,並通過位於接觸窗內的多個導電柱501a、501b而電性連接於晶片20的焊墊200以及第二導線層102。
之後,形成設置於內連線路層502上的第二上介電層503,且第二上介電層503具有至少一開孔(圖9繪示兩個為例),以暴露內連線路層502的部分表面。隨後,在開孔內可設置用以電性連接於外部電路的上方金屬焊墊504。據此,晶片20的每一個焊墊200可通過導電柱501a、501b以及內連線路層502,以電性連接於上方金屬焊墊504。
請參照圖10,本實施例中,形成導電散熱層40於晶片20的底面20b。導電散熱層40可以利用濺鍍、蒸鍍、化鍍或是電鍍來製作,或是前述不
同方法的組合來製作,本發明並不限制。
導電散熱層40設置並接觸於晶片20的底面20b,以將晶片20所產生的熱能有效地傳導至外部。導電散熱層40可以是單層或者是多層。當導電散熱層40為單層時,導電散熱層40的材料可以是金屬、合金或者其他導電材料。
當導電散熱層40為多層時,每一層的材料可以相同或者不同。舉例而言,導電散熱層40的材料可以由不同的金屬任意組合而成,例如:鈦、銅、鋅、鎳、銀、金、錫。另外,導電散熱層40可以是單層金屬或多層金屬組合而成。在本發明實施例中,導電散熱層40的厚度範圍是由10至50μm,以對晶片20有較佳的散熱效果。
由於本發明的導電散熱層40可以直接附著在晶片20上,且導電散熱層40與晶片20的底面20b之間幾乎不會產生空隙以及熱阻而影響散熱效果。據此,相較於僅以金屬材料或是有機複合散熱材料黏著或抵靠於晶片20的底面20b,本發明實施例的導電散熱層40可與晶片20相互密合,而對晶片20提供更好的散熱效果。
此外,形成下層重分布線路結構60的步驟至少包括:形成至少一下方金屬焊墊601以及一下介電層600。下方金屬焊墊601電性連接線路板10。進一步而言,下方金屬焊墊601是通過第一介電層103的第二開口圖案103p,以電性連接於第一導線層101。下介電層600位於線路板10的第一表面10a,並覆蓋一部分導電散熱層40以及一部分下方金屬焊墊601。下介電層600具有一散熱開口600a以及一焊墊開口600b,以分別裸露導電散熱層40的一部分,以及下方金屬焊墊601的一部分。
如此,導電散熱層40可通過散熱開口600a,以將晶片20所產生的熱能傳導至外部環境。此外,可分別在下介電層600的焊墊開口600b內設置
多個導電凸塊(bump)(圖未示),以使晶片封裝模組M1可設置並電性連接於另一電路板或者另一元件,如:另一晶片封裝模組。前述的導電凸塊可包括焊球以及球下金屬層(UBM)。
多個導電柱501a、501b、內連線路層502、第二上介電層503、上方金屬焊墊504以及下方金屬焊墊601的材料可以是金屬、合金或者複合導電材料。金屬或合金例如是由銅、銀、鎳、金、錫或其任意組合所組成的群組中的其中一種。另外,複合導電材料例如是銀膠或碳膠。
基於上述,如圖10所示,本發明實施例提供一種具散熱功能的晶片封裝模組M1,其至少包括:一線路板10、一晶片20、一膠材30以及一導電散熱層40。
線路板10具有一第一表面10a以及與第一表面10a相反的第二表面10b,且線路板10為具有多層結構的複合板。在本實施例中,線路板10至少包括核心基板100、第一導線層101、第二導線層102、第一介電層103以及第二介電層104。
第一導線層101與第二導線層102分別設置於核心基板100的兩相反側,並通過導電通孔100h而彼此電性連接。第一介電層103與第二介電層104分別設置在核心基板100的兩相反側。在本實施例中,第一介電層103與第二介電層104分別是線路板10的最外側兩層。
第一介電層103設置在第一導線層101上,並具有第一開口圖案103p,以裸露一部分第一導線層101。另外,第二介電層104設置在第二導線層102上,並具有一第二開口圖案104p,以裸露一部分第二導線層102。
如圖10所示,本發明實施例的線路板10具有一晶片容置空間100S,且晶片容置空間100S由線路板10的第一表面10a延伸至第二表面10b。晶片20設置在晶片容置空間100S內,也就是設置在線路板10內部。晶片20例
如,但不限於是,功率晶片、被動元件或是感測晶片。
值得注意的是,在本發明實施例中,晶片20的厚度會大致與線路板10的厚度相同。據此,晶片20的厚度會大於核心基板100的厚度。
晶片20具有一主動面20a以及與主動面20a相反的底面20b。另外,晶片20並具有位於主動面20a上的至少一焊墊200(圖10繪示兩個為例)。在本發明實施例中,晶片20的主動面20a與第二導線層102都面向相同方向設置。亦即,晶片20的焊墊200與第二導線層102都是位於核心基板100的相同側。
膠材30填充於晶片20的側表面20s與晶片容置空間100S的側壁之間,以使晶片20固定於線路板10。也就是說,膠材30是填入晶片20的側表面20s與晶片容置空間100S的側壁所定義的空隙內。據此,膠材30會圍繞並包覆晶片20至少一部份的側表面20s。
在本發明實施例中,膠材30會包覆晶片20的整個側表面20s,且膠材30的其中一表面(頂表面30a)會與線路板10的第二表面10b(也就是第二介電層104的外表面)共平面。另外,膠材30的另一表面30b與線路板10的第一表面10a(也就是第一介電層103的外表面)共平面。
值得注意的是,在本發明實施例中,膠材30只包覆晶片20的側表面20s,而不會覆蓋位於晶片20的主動面20a上的焊墊200。
請繼續參照圖10,導電散熱層40設置並接觸於晶片20的底面20b,以將晶片20所產生的熱能有效地傳導至外部。導電散熱層40的材料以及結構可參照前文敘述,在此不再贅述。
在本發明實施例中,導電散熱層40的厚度範圍是由10至50μm,以對晶片20有較佳的散熱效果。導電散熱層40可以直接附著在晶片20上,且導電散熱層40與晶片20的底面20b之間幾乎不會產生空隙以及熱阻,而可對晶片20提供更好的散熱效果。
另外,在本發明實施例中,具散熱功能的晶片封裝模組M1還進一步包括一上層重分布線路結構50。上層重分布線路結構50是設置於線路板10的第二表面10b上,並電性連接於晶片20,以使晶片20可電性連接於外部電路。
如前所述,上層重分布線路結構50包括第一上介電層500、多個導電柱501a、501b、內連線路層502、第二上介電層503。晶片20的每一個焊墊200可通過導電柱501a以及內連線路層502,以電性連接於上方金屬焊墊504。據此,另一元件可通過上方金屬焊墊504電性連接於晶片20。第一上介電層500、多個導電柱501a、501b、內連線路層502、第二上介電層503的詳細結構在此不再贅述。
具散熱功能的晶片封裝模組M1還進一步包括下層重分布線路結構60,其位於線路板10的第一表面10a。下層重分布線路結構60包括至少一下方金屬焊墊601以及下介電層600。
下方金屬焊墊601與導電散熱層40共同設置在線路板10的第一表面10a上。進一步而言,下方金屬焊墊601是通過第一介電層103的第一開口圖案103p,以電性連接於第一導線層101。
下介電層600位於線路板10的第一表面10a,並覆蓋一部分導電散熱層40以及一部分下方金屬焊墊601。進一步而言,下介電層600具有至少一散熱開口600a,以裸露出位於晶片20下方的一部分導電散熱層40。如此,導電散熱層40可通過散熱開口600a,以將晶片20所產生的熱能傳導至外部環境。
此外,下介電層600還具有至少一焊墊開口600b(圖10繪示兩個為例),以裸露出另一部分位於線路板10第一表面10a的下方金屬焊墊601。據此,可分別在下介電層600的焊墊開口600b內設置多個導電凸塊(bump)(圖未
示),以使晶片封裝模組M1可設置並電性連接於另一電路板或者另一元件,如:另一晶片封裝模組。前述的導電凸塊可包括焊球以及球下金屬層(UBM)。另一晶片封裝模組可以是晶片封裝模組、感測晶片封裝模組或者是被動晶片封裝模組,本發明並不限制。
[實施例的有益效果]
本發明的其中一有益效果在於,本發明所提供的具散熱功能的晶片封裝模組及其製造方法,其能通過“提供具有對位圖案P10的暫時性承載板P”,“根據對位圖案P10,將線路板10設置於暫時性承載板P上”以及“根據對位圖案P10,將一晶片20以主動面20a朝向暫時性承載板P而設置於晶片容置空間100S內”的技術手段,可以使線路板10與晶片20之間的對位更精準。如此,在後續形成上層重分布線路結構50以及下層重分布線路結構60時,可避免上層重分布線路結構50以及下層重分布線路結構60與晶片20之間相對位置改變,而導致短路或者斷路。
此外,本發明所提供的具散熱功能的晶片封裝模組及製造方法中,通過“導電散熱層40設置並接觸於晶片20的底面20b”的技術方案,可提升導電散熱層40對晶片20的散熱效果。更進一步來說,本發明實施例的導電散熱層40直接附著在晶片20上,且導電散熱層40與晶片20的底面20b之間不會產生空隙,而可對晶片20提供更好的散熱效果。
以上所公開的內容僅為本發明的優選可行實施例,並非因此侷限本發明的申請專利範圍,所以凡是運用本發明說明書及圖式內容所做的等效技術變化,均包含於本發明的申請專利範圍內。
S100~S150:步驟
Claims (15)
- 一種具散熱功能的晶片封裝模組的製造方法,其包括:提供一具有一對位圖案的暫時性承載板,所述暫時性承載板包括一底板以及設置於所述底板上的一可剝離黏著材料;根據所述對位圖案,將一線路板設置於所述暫時性承載板上,其中,所述線路板具有貫穿所述線路板的一晶片容置空間,所述線路板包括一核心基板、一第一導線層以及一第二導線層,所述第一導線層與所述第二導線層分別位於所述核心基板的兩相反側;根據所述對位圖案,將一晶片以主動面朝向所述暫時性承載板而設置於所述晶片容置空間內,其中,所述晶片通過所述可剝離黏著材料固定於所述暫時性承載板上,且所述晶片的厚度大於所述核心基板的厚度;填入一膠材於所述晶片容置空間內,以使所述晶片連接並固定於所述線路板,而形成一初始封裝體;分離所述初始封裝體以及所述暫時性承載板,其中,所述晶片的底面裸露於所述初始封裝體的底側;以及在所述初始封裝體的所述底側形成一導電散熱層,以直接接觸並覆蓋所述晶片的所述底面。
- 如申請專利範圍第1項所述的製造方法,其中,所述對位圖案包括至少一線路板對位標記以及至少一晶片對位標記,在設置所述線路板於所述暫時性承載板的步驟中,所述線路板對應於至少一所述線路板對位標記設置於所述暫時性承載板上,且至少一所述晶片對位標記由所述晶片容置空間裸露出來。
- 如申請專利範圍第1項所述的製造方法,其中,所述對位圖案 包括至少一晶片對位標記,所述晶片具有位於所述主動面上的至少一焊墊,且在將所述晶片設置於所述晶片容置空間內的步驟中,至少一所述焊墊對準於對應的至少一所述晶片對位標記而設置於所述暫時性承載板上。
- 如申請專利範圍第1項所述的製造方法,其中,所述晶片具有位於所述主動面上的至少一焊墊,當所述晶片設置於所述晶片容置空間內時,至少一所述焊墊的一部分埋入所述可剝離黏著材料內。
- 如申請專利範圍第1項所述的製造方法,其中,所述底板的材料以及所述可剝離黏著材料為透明材料。
- 如申請專利範圍第1項所述的製造方法,其中,所述線路板還包括一第一介電層以及一第二介電層,所述第一介電層覆蓋所述第一導線層,並具有一第一開口圖案,以裸露一部分所述第一導線層,且所述第二介電層設置在所述第二導線層上,並具有一第二開口圖案,以裸露一部分所述第二導線層。
- 如申請專利範圍第6項所述的製造方法,其中,所述第一介電層或所述第二介電層的材料為聚醯亞胺、苯丙環丁烯、矽膠或樹脂。
- 如申請專利範圍第1項所述的製造方法,還進一步包括:在填入所述膠材於所述晶片容置空間內的步驟之後,所述線路板的其中一表面與所述膠材的其中一表面共平面。
- 如申請專利範圍第1項所述的製造方法,還進一步包括:在所述初始封裝體的所述底側形成一下層重分布線路結構;以及在所述初始封裝體的一頂側形成一上層重分布線路結構。
- 如申請專利範圍第9項所述的製造方法,其中,形成所述下層重分布線路結構的步驟至少包括:形成至少一下方金屬焊墊以及一下介電層,其中,所述下方金屬焊墊電性連接於所述線路板,且所述下介電層具有一散熱開口以及一焊墊開口,以分別裸露所述導電散熱層的一部分以及裸露所述下方金屬焊墊的一部分。
- 一種具散熱功能的晶片封裝模組,其包括:一線路板,其具有一貫穿所述線路板的一晶片容置空間,其中,所述線路板包括一核心基板、一第一導線層以及一第二導線層,所述第一導線層與所述第二導線層分別位於所述核心基板的兩相反側;一晶片,其設置在所述晶片容置空間內,所述晶片具有一主動面以及與所述主動面相反的一底面,其中,所述晶片的厚度大於所述核心基板的厚度;一膠材,其填充於所述晶片的側表面與所述晶片容置空間的側壁之間,以使所述晶片固定於所述線路板;以及一導電散熱層,其設置並接觸於所述晶片的所述底面。
- 如申請專利範圍第11項所述的具散熱功能的晶片封裝模組,其中,所述晶片具有設置於所述主動面的至少一焊墊,所述焊墊 與所述第二導線層位於相同側。
- 如申請專利範圍第12項所述的具散熱功能的晶片封裝模組,其中,所述線路板還包括一第一介電層以及一第二介電層,所述第一介電層覆蓋所述第一導線層,並具有一第一開口圖案,以裸露一部分所述第一導線層,且所述第二介電層設置在所述第二導線層上,並具有一第二開口圖案,以裸露一部分所述第二導線層。
- 如申請專利範圍第11項所述的具散熱功能的晶片封裝模組,其中,所述導電散熱層的厚度範圍是由10至50μm。
- 如申請專利範圍第11項所述的具散熱功能的晶片封裝模組,還進一步包括:一下層重分布線路結構,其中,所述下層重分布線路結構與所述導電散熱層位於所述線路板的相同側,且所述下層重分布線路結構具有至少一散熱開口,以裸露所述導電散熱層的一部分。
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