SE449941B - Anordning for synkronisering av fasleget for en lokal klocksignal med fasleget for en insignal - Google Patents
Anordning for synkronisering av fasleget for en lokal klocksignal med fasleget for en insignalInfo
- Publication number
- SE449941B SE449941B SE8100527A SE8100527A SE449941B SE 449941 B SE449941 B SE 449941B SE 8100527 A SE8100527 A SE 8100527A SE 8100527 A SE8100527 A SE 8100527A SE 449941 B SE449941 B SE 449941B
- Authority
- SE
- Sweden
- Prior art keywords
- input
- flip
- circuit
- output
- flops
- Prior art date
Links
- 230000001960 triggered effect Effects 0.000 claims description 7
- 239000013078 crystal Substances 0.000 description 4
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NLAANVRAGE8000606,A NL183214C (nl) | 1980-01-31 | 1980-01-31 | Inrichting voor het synchroniseren van de fase van een lokaal opgewekt kloksignaal met de fase van een ingangssignaal. |
Publications (1)
Publication Number | Publication Date |
---|---|
SE449941B true SE449941B (sv) | 1987-05-25 |
Family
ID=19834765
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE8100527D SE8100527L (sv) | 1980-01-31 | 1981-01-28 | Anordning for synkronisering av fasleget for en lokal klocksignal med en insignal |
SE8100527A SE449941B (sv) | 1980-01-31 | 1981-01-28 | Anordning for synkronisering av fasleget for en lokal klocksignal med fasleget for en insignal |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE8100527D SE8100527L (sv) | 1980-01-31 | 1981-01-28 | Anordning for synkronisering av fasleget for en lokal klocksignal med en insignal |
Country Status (9)
Country | Link |
---|---|
US (1) | US4386323A (de) |
JP (1) | JPS56120227A (de) |
BE (1) | BE887296A (de) |
CA (1) | CA1155932A (de) |
DE (1) | DE3102447A1 (de) |
FR (1) | FR2475318A1 (de) |
GB (1) | GB2069263B (de) |
NL (1) | NL183214C (de) |
SE (2) | SE8100527L (de) |
Families Citing this family (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3173313D1 (en) * | 1980-09-25 | 1986-02-06 | Toshiba Kk | Clock synchronization signal generating circuit |
US4525674A (en) * | 1982-07-28 | 1985-06-25 | Reliance Electric Company | Circuit for synchronizing a switching power supply to a load clock |
JPS5986385A (ja) * | 1982-11-09 | 1984-05-18 | Toshiba Corp | サンプリングパルス生成回路 |
US4617679A (en) * | 1983-09-20 | 1986-10-14 | Nec Electronics U.S.A., Inc. | Digital phase lock loop circuit |
JPS60143017A (ja) * | 1983-12-29 | 1985-07-29 | Advantest Corp | クロツク同期式論理装置 |
US4575860A (en) * | 1984-03-12 | 1986-03-11 | At&T Bell Laboratories | Data clock recovery circuit |
JPS60204121A (ja) * | 1984-03-29 | 1985-10-15 | Fujitsu Ltd | 位相同期回路 |
DE3481472D1 (de) * | 1984-12-21 | 1990-04-05 | Ibm | Digitale phasenregelschleife. |
US4604582A (en) * | 1985-01-04 | 1986-08-05 | Lockheed Electronics Company, Inc. | Digital phase correlator |
US4635249A (en) * | 1985-05-03 | 1987-01-06 | At&T Information Systems Inc. | Glitchless clock signal control circuit for a duplicated system |
US4675612A (en) * | 1985-06-21 | 1987-06-23 | Advanced Micro Devices, Inc. | Apparatus for synchronization of a first signal with a second signal |
US4654599A (en) * | 1985-07-05 | 1987-03-31 | Sperry Corporation | Four phase clock signal generator |
US4787095A (en) * | 1987-03-03 | 1988-11-22 | Advanced Micro Devices, Inc. | Preamble search and synchronizer circuit |
US4791488A (en) * | 1987-08-12 | 1988-12-13 | Rca Licensing Corporation | Line-locked clock signal generation system |
US4757264A (en) * | 1987-10-08 | 1988-07-12 | American Telephone And Telegraph Company, At&T Bell Laboratories | Sample clock signal generator circuit |
JPH0795731B2 (ja) * | 1987-10-30 | 1995-10-11 | 株式会社ケンウッド | データ受信装置の最適クロック形成装置 |
US4868514A (en) * | 1987-11-17 | 1989-09-19 | International Business Machines Corporation | Apparatus and method for digital compensation of oscillator drift |
JPH01149516A (ja) * | 1987-12-04 | 1989-06-12 | Mitsubishi Electric Corp | クロック発生装置 |
US5022057A (en) * | 1988-03-11 | 1991-06-04 | Hitachi, Ltd. | Bit synchronization circuit |
ATE76706T1 (de) * | 1988-03-22 | 1992-06-15 | Siemens Ag | Verfahren und anordnung zur fortlaufenden anpassung der phase eines binaeren datensignals an einen takt. |
EP0339515B1 (de) * | 1988-04-29 | 1992-12-23 | Siemens Aktiengesellschaft | Verfahren und Anordnung zur Taktrückgewinnung aus einem Datensignal durch fortlaufende Anpassung eines örtlich erzeugten Taktes an ein Datensignal |
US5050189A (en) * | 1988-11-14 | 1991-09-17 | Datapoint Corporation | Multibit amplitude and phase modulation transceiver for LAN |
US5034967A (en) * | 1988-11-14 | 1991-07-23 | Datapoint Corporation | Metastable-free digital synchronizer with low phase error |
US5008879B1 (en) * | 1988-11-14 | 2000-05-30 | Datapoint Corp | Lan with interoperative multiple operational capabilities |
US5048014A (en) * | 1988-12-30 | 1991-09-10 | Datapoint Corporation | Dynamic network reconfiguration technique for directed-token expanded-address LAN |
US4908842A (en) * | 1989-02-14 | 1990-03-13 | Galen Collins | Flash synchronized gated sample clock generator |
ATE110505T1 (de) * | 1989-02-23 | 1994-09-15 | Siemens Ag | Verfahren und anordnung zum anpassen eines taktes an ein plesiochrones datensignal und zu dessen abtakten mit dem angepassten takt. |
US5424882A (en) * | 1989-03-13 | 1995-06-13 | Hitachi, Ltd. | Signal processor for discriminating recording data |
US5267267A (en) * | 1989-03-13 | 1993-11-30 | Hitachi, Ltd. | Timing extraction method and communication system |
JP2664249B2 (ja) * | 1989-03-13 | 1997-10-15 | 株式会社日立製作所 | タイミング抽出回路,それを利用した通信システム及びタイミング抽出方法並びに通信装置 |
JP2536929B2 (ja) * | 1989-07-21 | 1996-09-25 | 富士通株式会社 | 位相整合回路 |
DE3931259A1 (de) * | 1989-09-19 | 1991-03-28 | Siemens Ag | Verfahren zur fortlaufenden anpassung der phase eines digitalsignals an einen takt |
US4998264A (en) * | 1989-09-20 | 1991-03-05 | Data Broadcasting Corporation | Method and apparatus for recovering data, such as teletext data encoded into television signals |
DE3936901A1 (de) * | 1989-11-06 | 1991-05-23 | Ant Nachrichtentech | Halbleiterchip mit mehreren schieberegistern |
US5109394A (en) * | 1990-12-24 | 1992-04-28 | Ncr Corporation | All digital phase locked loop |
US5212716A (en) * | 1991-02-05 | 1993-05-18 | International Business Machines Corporation | Data edge phase sorting circuits |
JPH0778774B2 (ja) * | 1991-02-22 | 1995-08-23 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 短待ち時間データ回復装置及びメッセージデータの同期化方法 |
US5255292A (en) * | 1992-03-27 | 1993-10-19 | Motorola, Inc. | Method and apparatus for modifying a decision-directed clock recovery system |
EP0608578B1 (de) * | 1993-01-28 | 1998-08-26 | Alcatel | Synchronisierungsschaltung |
US5412698A (en) * | 1993-03-16 | 1995-05-02 | Apple Computer, Inc. | Adaptive data separator |
EP0648033B1 (de) * | 1993-10-12 | 2002-09-25 | Alcatel | Synchronisierungsschaltung |
JPH08111675A (ja) * | 1994-10-07 | 1996-04-30 | Mitsubishi Denki Eng Kk | 同期回路 |
US6239627B1 (en) * | 1995-01-03 | 2001-05-29 | Via-Cyrix, Inc. | Clock multiplier using nonoverlapping clock pulses for waveform generation |
US5646568A (en) * | 1995-02-28 | 1997-07-08 | Ando Electric Co., Ltd. | Delay circuit |
US6064707A (en) * | 1995-12-22 | 2000-05-16 | Zilog, Inc. | Apparatus and method for data synchronizing and tracking |
KR100197563B1 (ko) * | 1995-12-27 | 1999-06-15 | 윤종용 | 동기 지연라인을 이용한 디지탈 지연 동기루프 회로 |
WO1998004043A1 (en) * | 1996-07-23 | 1998-01-29 | Honeywell Inc. | High resolution digital synchronization circuit |
US6043694A (en) * | 1998-06-24 | 2000-03-28 | Siemens Aktiengesellschaft | Lock arrangement for a calibrated DLL in DDR SDRAM applications |
JP3394013B2 (ja) * | 1999-12-24 | 2003-04-07 | 松下電器産業株式会社 | データ抽出回路およびデータ抽出システム |
US7253671B2 (en) * | 2004-06-28 | 2007-08-07 | Intelliserv, Inc. | Apparatus and method for compensating for clock drift in downhole drilling components |
US9384818B2 (en) * | 2005-04-21 | 2016-07-05 | Violin Memory | Memory power management |
US9582449B2 (en) | 2005-04-21 | 2017-02-28 | Violin Memory, Inc. | Interconnection system |
JP2008537265A (ja) * | 2005-04-21 | 2008-09-11 | ヴァイオリン メモリー インコーポレイテッド | 相互接続システム |
US8452929B2 (en) * | 2005-04-21 | 2013-05-28 | Violin Memory Inc. | Method and system for storage of data in non-volatile media |
US8112655B2 (en) * | 2005-04-21 | 2012-02-07 | Violin Memory, Inc. | Mesosynchronous data bus apparatus and method of data transmission |
US9286198B2 (en) | 2005-04-21 | 2016-03-15 | Violin Memory | Method and system for storage of data in non-volatile media |
US8028186B2 (en) * | 2006-10-23 | 2011-09-27 | Violin Memory, Inc. | Skew management in an interconnection system |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3029389A (en) * | 1960-04-20 | 1962-04-10 | Ibm | Frequency shifting self-synchronizing clock |
FR1422959A (fr) * | 1964-11-13 | 1966-01-03 | Thomson Houston Comp Francaise | Perfectionnements aux dispositifs d'asservissement en phase |
US3509471A (en) * | 1966-11-16 | 1970-04-28 | Communications Satellite Corp | Digital phase lock loop for bit timing recovery |
US4169995A (en) * | 1970-01-21 | 1979-10-02 | The United States Of America As Represented By The Secretary Of The Air Force | Pulse repetition frequency tracker |
US3763317A (en) * | 1970-04-01 | 1973-10-02 | Ampex | System for correcting time-base errors in a repetitive signal |
FR2283592A1 (fr) * | 1974-08-27 | 1976-03-26 | Thomson Csf | Dispositif extracteur de synchronisation et systeme de transmission d'informations comportant un tel dispositif |
JPS5563123A (en) * | 1978-11-04 | 1980-05-13 | Sony Corp | Phase control circuit |
-
1980
- 1980-01-31 NL NLAANVRAGE8000606,A patent/NL183214C/xx not_active IP Right Cessation
-
1981
- 1981-01-22 CA CA000369102A patent/CA1155932A/en not_active Expired
- 1981-01-23 US US06/227,892 patent/US4386323A/en not_active Expired - Fee Related
- 1981-01-26 DE DE19813102447 patent/DE3102447A1/de active Granted
- 1981-01-26 FR FR8101381A patent/FR2475318A1/fr active Granted
- 1981-01-28 GB GB8102580A patent/GB2069263B/en not_active Expired
- 1981-01-28 SE SE8100527D patent/SE8100527L/xx not_active Application Discontinuation
- 1981-01-28 SE SE8100527A patent/SE449941B/sv not_active IP Right Cessation
- 1981-01-28 JP JP1032681A patent/JPS56120227A/ja active Pending
- 1981-01-29 BE BE0/203645A patent/BE887296A/fr not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
BE887296A (fr) | 1981-07-29 |
CA1155932A (en) | 1983-10-25 |
DE3102447A1 (de) | 1981-11-19 |
FR2475318A1 (fr) | 1981-08-07 |
NL183214B (nl) | 1988-03-16 |
SE8100527L (sv) | 1981-08-01 |
NL183214C (nl) | 1988-08-16 |
US4386323A (en) | 1983-05-31 |
DE3102447C2 (de) | 1989-05-11 |
GB2069263B (en) | 1983-11-30 |
GB2069263A (en) | 1981-08-19 |
NL8000606A (nl) | 1981-09-01 |
FR2475318B1 (de) | 1984-05-11 |
JPS56120227A (en) | 1981-09-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
SE449941B (sv) | Anordning for synkronisering av fasleget for en lokal klocksignal med fasleget for en insignal | |
KR100528379B1 (ko) | 클록신호분배시스템 | |
EP0903885B1 (de) | Taktrückgewinnungsschaltung | |
EP0596657A2 (de) | Normalisierung der sichtbaren Fortpflanzungsverzögerung | |
JPS60227541A (ja) | ディジタルpll回路 | |
KR960019983A (ko) | 가변 지연회로 | |
KR970701950A (ko) | 비교기 입력 스와핑 기법을 사용하는 위상 오차 처리기 회로(a phase error processor circuit with a comparator input swapping technique) | |
KR0165683B1 (ko) | 동기 회로 | |
US5003308A (en) | Serial data receiver with phase shift detection | |
SE511852C2 (sv) | Klockfasjusterare för återvinning av datapulser | |
US6208182B1 (en) | Phase-locked loop circuit | |
US5929676A (en) | Asynchronous pulse discriminating synchronizing clock pulse generator for logic derived clock signals for a programmable device | |
US7937608B2 (en) | Clock generating circuit and digital circuit system incorporating the same | |
US5912573A (en) | Synchronizing clock pulse generator for logic derived clock signals for a programmable device | |
JP3132657B2 (ja) | クロック切替回路 | |
US6885714B1 (en) | Independently roving range control | |
SU1182625A1 (ru) | Частотно-фазовый дискриминатор | |
SU661813A1 (ru) | Перестраивающий делитель частоты | |
JP3193890B2 (ja) | ビット同期回路 | |
SU842825A1 (ru) | Устройство дл синхронизации двух-пРОцЕССОРНОй СиСТЕМы ОбРАбОТКидАННыХ | |
KR100246340B1 (ko) | 디지탈 지연 고정 루프장치 | |
SU1495905A1 (ru) | Устройство дл синхронизации генераторов переменного тока | |
SU1626429A1 (ru) | Фазокорректирующее устройство | |
JPH04207520A (ja) | 非同期クロックパルスの同期化方式 | |
JPH0738398A (ja) | クロック切替回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
NUG | Patent has lapsed |
Ref document number: 8100527-4 Effective date: 19901211 |