KR960701467A - 알루미늄-게르마늄 합금을 사용하는 바이어스 및 접촉부 충전(Filling of vias and contacts employing an aluminum-germanium alloy) - Google Patents
알루미늄-게르마늄 합금을 사용하는 바이어스 및 접촉부 충전(Filling of vias and contacts employing an aluminum-germanium alloy) Download PDFInfo
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- KR960701467A KR960701467A KR1019950703443A KR19950703443A KR960701467A KR 960701467 A KR960701467 A KR 960701467A KR 1019950703443 A KR1019950703443 A KR 1019950703443A KR 19950703443 A KR19950703443 A KR 19950703443A KR 960701467 A KR960701467 A KR 960701467A
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- Prior art keywords
- aluminum
- layer
- germanium
- deposited
- temperature
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53219—Aluminium alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
Abstract
초미세한 바이어스를 알루미늄으로써 충전시키는 다단계 방법은 약 150℃ 온도에서 스피터 증착되는 약 1000옹그스트롱인 알루미늄의 초기 증착을 포함함. 연속해서, 알루미늄 게르마늄 합금층이 다시 150℃ 이하에서 약 1000 옹그스트롱으로 증착된다. 게르마늄 없는 알루미늄의 제3층은 약 150℃ 온도에서 증착된다. 대략 1000 옹그스트롱이 증착된다. 그것은 전체적으로 5000 내지 15000 옹그스트롱인 알루미늄을 증착시키기 위해 450℃ 내지 500℃에서 행해지는 최종 알루미늄 증착에 의해 뒤다라진다. 상대적으로 저온인 150℃에서 2개의 알루미늄 증착은 게르마늄으로 하여금 침전되는 것을 방지하고 게르마늄으로 하여금 중착된 금속의 모든 용해 온도를 증가시키는 상기 층으로 확산되게 하여 연속적인 고치리 온도에서 금속이 바이어스 표면을 디웨트(dewet) 하지 않는다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
Claims (7)
- 반도체 기판에서의 바이어스 충전(filling) 방법에 있어서, 알루미늄을 함유하는 비게르마늄(nongermanium)의 제1층을 150℃ 이하인 온도에서 상기 바이어스를 함유하는 기판상에 스피터 증착시키는 단계와, 알루미늄-게르마늄 합금층을 150℃ 이하인 온도에서 스피터 증착시키는 단계와, 제2층이 1000옹그스토롱 두께이고 150℃이하에서 증착될 때, 알루미늄 층을 함유하는 비게르마늄의 상기 제2층을 스피터 증착시키는 단계와, 알루미늄을 함유하는 비게르마늄의 상기 제3층을 400 내지 500℃ 온도에서 상기 기판에 증착시키는 단계를 구비하며, 상기 층 모두의 총 두께가 약 50000 내지 15000옹그스트롱인 것을 특징으로 하는 반도체 기판에서의 바이어스 충전 방법.
- 제1항에 있어서, 합금을 함유한 상기 게르마늄은 약 1 내지 5%인 게르마늄을 구비하는 것을 특징으로 하는 반도체 기판에서의 바이어스 충전 방법.
- 제1항에 있어서, 상기 알루미늄-게르마늄 합금이 10 내지 15킬로와트의 인가된 전력으로써 150℃이하인 온도에서 증착되는 것을 특징으로 하는 반도체 기판에서의 바이어스 충전 방법.
- 제1항에 있어서, 상기 제1층이 약 1000 옹그스트롱 두께인 것을 특징으로 하는 반도체 기판에서의 바이어스 충전 방법.
- 제2항에 있어서, 알루미늄의 상기 초기 증착이 조준기를 통해 행해지는 것을 특징으로 하는 반도체 기판에서의 바이어스 충전 방법.
- 제5항에 있어서, 알루미늄-게르마늄 합금의 상기 증착이 조준기를 통해 행해지는 것을 특징으로 하는 반도체 기판에서의 바이어스 충전 방법.
- 제1항에 있어서, 상기 제3층이 1 내지 2분 주기 동안 증착된 후, 상기 기판이 온도 450℃ 내지 500℃로 유지되는 것을 특징으로 하는 반도체 기판에서의 바이어스 충전 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/018,769 US5358616A (en) | 1993-02-17 | 1993-02-17 | Filling of vias and contacts employing an aluminum-germanium alloy |
US018,769 | 1993-02-17 | ||
PCT/US1994/000309 WO1994019826A1 (en) | 1993-02-17 | 1994-01-10 | Filling of vias and contacts employing an aluminum-germanium alloy |
Publications (1)
Publication Number | Publication Date |
---|---|
KR960701467A true KR960701467A (ko) | 1996-02-24 |
Family
ID=21789696
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950703443A KR960701467A (ko) | 1993-02-17 | 1994-01-10 | 알루미늄-게르마늄 합금을 사용하는 바이어스 및 접촉부 충전(Filling of vias and contacts employing an aluminum-germanium alloy) |
Country Status (8)
Country | Link |
---|---|
US (1) | US5358616A (ko) |
EP (1) | EP0685114A1 (ko) |
JP (1) | JPH08506935A (ko) |
KR (1) | KR960701467A (ko) |
AU (1) | AU5993994A (ko) |
CA (1) | CA2153680A1 (ko) |
TW (1) | TW243535B (ko) |
WO (1) | WO1994019826A1 (ko) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5747360A (en) * | 1993-09-17 | 1998-05-05 | Applied Materials, Inc. | Method of metalizing a semiconductor wafer |
TW298674B (ko) * | 1995-07-07 | 1997-02-21 | At & T Corp | |
US6239029B1 (en) | 1995-07-17 | 2001-05-29 | Micron Technology, Inc. | Sacrificial germanium layer for formation of a contact |
US5644166A (en) | 1995-07-17 | 1997-07-01 | Micron Technology, Inc. | Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts |
US6238533B1 (en) * | 1995-08-07 | 2001-05-29 | Applied Materials, Inc. | Integrated PVD system for aluminum hole filling using ionized metal adhesion layer |
US5962923A (en) * | 1995-08-07 | 1999-10-05 | Applied Materials, Inc. | Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches |
US5633199A (en) * | 1995-11-02 | 1997-05-27 | Motorola Inc. | Process for fabricating a metallized interconnect structure in a semiconductor device |
US5851920A (en) * | 1996-01-22 | 1998-12-22 | Motorola, Inc. | Method of fabrication of metallization system |
US5789317A (en) | 1996-04-12 | 1998-08-04 | Micron Technology, Inc. | Low temperature reflow method for filling high aspect ratio contacts |
KR100223332B1 (ko) * | 1996-06-17 | 1999-10-15 | 김영환 | 반도체 소자의 금속배선 및 그 형성방법 |
US6331482B1 (en) | 1996-06-26 | 2001-12-18 | Micron Technology, Inc. | Method of VLSI contact, trench, and via filling using a germanium underlayer with metallization |
US5827408A (en) * | 1996-07-26 | 1998-10-27 | Applied Materials, Inc | Method and apparatus for improving the conformality of sputter deposited films |
US6309971B1 (en) | 1996-08-01 | 2001-10-30 | Cypress Semiconductor Corporation | Hot metallization process |
US5956612A (en) * | 1996-08-09 | 1999-09-21 | Micron Technology, Inc. | Trench/hole fill processes for semiconductor fabrication |
GB9619461D0 (en) * | 1996-09-18 | 1996-10-30 | Electrotech Ltd | Method of processing a workpiece |
US5873983A (en) * | 1997-01-13 | 1999-02-23 | Vanguard International Semiconductor Corporation | Method for minimizing substrate to clamp sticking during thermal processing of thermally flowable layers |
US6139698A (en) * | 1997-02-03 | 2000-10-31 | Applied Materials, Inc. | Method and apparatus for reducing the first wafer effect |
US6140228A (en) | 1997-11-13 | 2000-10-31 | Cypress Semiconductor Corporation | Low temperature metallization process |
US7253109B2 (en) | 1997-11-26 | 2007-08-07 | Applied Materials, Inc. | Method of depositing a tantalum nitride/tantalum diffusion barrier layer system |
JP4947834B2 (ja) * | 1997-11-26 | 2012-06-06 | アプライド マテリアルズ インコーポレイテッド | ダメージフリー被覆刻設堆積法 |
US6455427B1 (en) | 1999-12-30 | 2002-09-24 | Cypress Semiconductor Corp. | Method for forming void-free metallization in an integrated circuit |
US6969448B1 (en) | 1999-12-30 | 2005-11-29 | Cypress Semiconductor Corp. | Method for forming a metallization structure in an integrated circuit |
US6585870B1 (en) | 2000-04-28 | 2003-07-01 | Honeywell International Inc. | Physical vapor deposition targets having crystallographic orientations |
DE10032792A1 (de) * | 2000-06-28 | 2002-01-17 | Infineon Technologies Ag | Verfahren zur Herstellung einer Verdrahtung für Kontaktlöcher |
SE534488C2 (sv) | 2010-02-22 | 2011-09-06 | Lunavation Ab | Ett system för elektrokinetisk flödesteknik |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR900001825B1 (ko) * | 1984-11-14 | 1990-03-24 | 가부시끼가이샤 히다찌세이사꾸쇼 | 성막 지향성을 고려한 스퍼터링장치 |
JP2515731B2 (ja) * | 1985-10-25 | 1996-07-10 | 株式会社日立製作所 | 薄膜形成装置および薄膜形成方法 |
US4824544A (en) * | 1987-10-29 | 1989-04-25 | International Business Machines Corporation | Large area cathode lift-off sputter deposition device |
US4994162A (en) * | 1989-09-29 | 1991-02-19 | Materials Research Corporation | Planarization method |
US4970176A (en) * | 1989-09-29 | 1990-11-13 | Motorola, Inc. | Multiple step metallization process |
US5108570A (en) * | 1990-03-30 | 1992-04-28 | Applied Materials, Inc. | Multistep sputtering process for forming aluminum layer over stepped semiconductor wafer |
JP2601020B2 (ja) * | 1990-11-28 | 1997-04-16 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5171412A (en) * | 1991-08-23 | 1992-12-15 | Applied Materials, Inc. | Material deposition method for integrated circuit manufacturing |
-
1993
- 1993-02-17 US US08/018,769 patent/US5358616A/en not_active Expired - Lifetime
-
1994
- 1994-01-10 EP EP94906060A patent/EP0685114A1/en not_active Withdrawn
- 1994-01-10 AU AU59939/94A patent/AU5993994A/en not_active Abandoned
- 1994-01-10 CA CA002153680A patent/CA2153680A1/en not_active Abandoned
- 1994-01-10 JP JP6518954A patent/JPH08506935A/ja active Pending
- 1994-01-10 WO PCT/US1994/000309 patent/WO1994019826A1/en not_active Application Discontinuation
- 1994-01-10 KR KR1019950703443A patent/KR960701467A/ko not_active Application Discontinuation
- 1994-01-12 TW TW083100204A patent/TW243535B/zh active
Also Published As
Publication number | Publication date |
---|---|
CA2153680A1 (en) | 1994-09-01 |
TW243535B (ko) | 1995-03-21 |
EP0685114A1 (en) | 1995-12-06 |
WO1994019826A1 (en) | 1994-09-01 |
US5358616A (en) | 1994-10-25 |
JPH08506935A (ja) | 1996-07-23 |
AU5993994A (en) | 1994-09-14 |
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