TW243535B - - Google Patents
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- TW243535B TW243535B TW083100204A TW83100204A TW243535B TW 243535 B TW243535 B TW 243535B TW 083100204 A TW083100204 A TW 083100204A TW 83100204 A TW83100204 A TW 83100204A TW 243535 B TW243535 B TW 243535B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53219—Aluminium alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
Description
Α6 Β6 43535 五、發明説明(1 ) 發明夕背暑 積體電路之有源開闞元件係Μ各種方法*如物理氣相沈 積、化學氧相沈積及蒸發法所沈積之金靥線互連。通常’ 於積體電路中使用數個位準之金靨線Μ使其交越。在某些 固定位置,於不同位準之線間會發生電接觸。此等位置稱 通孔。積髖電路演進至次微米大小造成通孔及觸點具相當 之寬高比及尺寸。以導電金屬填充次微米通孔及觸點相當 困難。然而,若不相當小心,會留下空隙並且必須丟棄晶 Η ° 用鋁作為填充互連通孔及觸點之材料已有提出。其於約 450 t:之溫度藉表面擴散使噴鍍沈積之鋁移入通孔°例如 ,此法揭示於阿姆斯壯(Armstrong)之美國專利案 4,994,162號。此係使用一低溫晶種層,提供一連續、儍 質之擴散路徑,使随後沈積之材枓沿此擴散。先用高溫低 沈積速率步嫌使有效表面擴散移入該部份,接著用一 高沈積速率步驟而完成沈積。 熟知之鋁準直噴鍍沈積揭示於,例如密卡列紳 (»<[1^1^611)等人之美國專利案 4,824,544號、厚_ (Houma)等人之美國專利案 4,7 1 7, 462號及沙卡塔 (Sakata)等人之美國專利案4,724,060號。厚瑪及沙卡$ 參考文獻特別使用鋁準直噴鍍填充具相當高寬高 Ο
Μ體擴散為通孔填充機構已由蘇加諾(Sugano)等人K 1992 VHIC 會議錄(Conference Proceedings)之”Μ ί呂之 本紙張尺度適用中國國家標準(CNS)甲4規格(210X297公釐Ϊ (請先閲讀背面之注意事項再填寫本頁) .裝 ,訂. 經濟部中央桴導局3工消费合作社印製 243535 五、發明説明(2 ) 高溫噴镀填充具S i N側壁之四分之一微米孔。蘇加諾方法 中,通孔填充之驅動力為钛表面層與沈積鋁間之界面。此 方法須存有連續且優質之钛表面層於通孔之側壁上。 崔西(Tracy)之美國專利案 4,970, 1 76揭示,於初始溫 度沈積一較厚之鋁層,且陲後於較高溫度沈積一鋁薄層。 此說明書指出溫度增加可使鋁藉晶粒成長及再結晶而逆流 。如該說明書所示,通孔之填充開始自通孔之底端,接著 上昇至頂端。於崔西申請案提出時期*其通孔通常具大於 一微米之大小。 低溫噴鍍沈積鋁會增加逐步覆蓋之可靠性•但於逐步覆 蓋整體性有強烈損失。此係因在小於300 t:之溫度,鋁移 動率微不足道之故。使用低熔點之鋁合金可降低有顯著移 動率所須之溫度。然而使用此合金時有數個問題。由於此 等合金之熔化溫度低,故其不可能抗拒隨後作桊步驟之溫 度。鋁一緒合金中之緒有析出傾向而增加抗性。 t請先閲讀背面之注意事項再蜞寫本頁) .裝 .訂 沭 槪 之 明0 Μ 地 靠 可 且 效 有 可 點 觸 及 孔 通 現 實 為。 係充 出填 提積 之沈 明鍍 發噴 本之 鋁 崚濟部中夬桴肀局=:工消費合作社印製 溫金 低合 於结 括 I 包絕 I 之 法層 積薄 沈一 驟積 步沈 多次 1 再 用著 利接 明。 發鋁 本之 ’ 層 之薄 言 一 佃積 詳沈 更步 初 第散方 積擴積 沈面沈 溫表層 低鋁多 於之此 後積用 随沈使 . 所 二 法 使 ’ 可 濕 其 沾 /(V 被 度 不 溫 面 高 表 較 點 於。觸 著層或 接鋁孔 。終通 鋁最免 之槙避 層沈可 本纸張尺度適用中國國家標準(CNS)甲4规格(210x297公釐) A6 B6 243335 五、發明説明(3 ) 並可發生沈積層之表面擴散,而填充通孔或觸點。 本發明之目的及優點可根據下列詳细說明中進一步察覺 本發明係闞於一 次微米直徑者,其 約1至約4。進行本 、通常1至約0 . 3微 孔及觸點可合併簡 本發明為一四一 薄層之鋁。第二步 。然後再於低溫沈 厚層之鋁。最終溫 擴散且平面化。 含有依本發明法 、摻雜質之氧化矽 詳鈕說明 填充通孔及觸點之方 通孔之寬高比(亦即 發明時,可填充具直 米之通孔及觸點。依 稱通孔。 步驟法。第一步,於 ,再於低溫Μ噴鍍沈 積第三層之鋁。接著 度維持於約500 Ό以 塗覆通孔之底材包括 底材、石英底材及砷 法,且特指該等具 高度/直徑比)為 徑為1至約0 . 1微米 本發明之目的*通 低溫以噴鍍沈積一 積一鋁-錯合金層 於較高溫度沈積一 使沈積之鋁層表面 矽底材、三氟化硼 化鎵底材。所形成 (請先閲讀背面之注意事項再填寫本頁) .裝 .訂. 校濟部中央標肀局8工消费合作杜印製 之鋁層可為100¾鋁及鋁合金,如鋁一矽(U) —銅(0.5¾)、 鋁-銅(1¾)及鋁-钛(0.15¾)。 初步沈積一薄層之鋁可在低於150TC下進行,且沈積層 小於或等於約1 0 0 0埃。 第二步,沈積一鋁一緒合金。該鋁一緒合金意即包括具 緒含量1 一5重量百分比之AlGe、AlSiGe、AlCuSiGe 。再 於低於或等於150¾之較低溫沈積此鋁一緒合金。僅約 本紙張尺度適用中國國家標準(CNS)甲4规格(210X297公釐) £43335 A6 _______B6 五、發明説明(4 ) 1000埃之鋁一I者合金受沈積。 第三步•於約1 50 t之低速率下沈積小於或等於約 1000埃之鋁或鋁合金(不含緒)。於沈積約〗〇〇〇埃之材料 後,溫度增加至約500°c,且沈積約5000至1 5, 000埃之絕 (請先閲讀背面之注意事項再蜞寫本頁) 噔濟部中央標苹局1=:工消費合作社印^ 於起初三次沈積之組層,鋁睹層及次一鋁層中,所有沈 積可在有或無準直器之輔肋下進行。由於鋁一结層夾於紹 層之間,可減少或避免緒之析出。再者,於随後作業中, 緒可進人各鋁層,當鋁接著繼續沈積時可增加其熔化溫度 且減少不沾濕之可能性。 本發明之多步沈積於多室噴鍍裝置中進行較佳,其可包 括一蝕刻室及至少三個噴鍍室。此一機器為由材料研究公 司所售、商標名現已失色之噴鍍系統,亦可參見美國專利 案4,994,162號。其他商用糸統同樣適用。 於第一反應室中,以氬氣使底材或晶片初蝕刻以除去表 面雜質。底材之加熱有肋於排放除氣。可視需要為之,但 有較佳。然後將底材轉送至第二反應室,若須要可使用阻 撞層。雖然氮化锆、氧化釕胆擋層亦可,但氮化鈦及钛轉 為較佳之阻擋層。通常阻擋層之厚度可為約1〇〇〇埃。 接著,將晶片轉送至第三反應室,其可包括或不包括準 直器,視需要而定。若使用準直器,較佳之寬高比為1至 2 。再者,即使不需要準直器,有仍較佳。此步驟中,鋁 或不含緒之鋁合金在低於150C之溫度Μ唄鍍沈積。靶上 之外施電力可自約10至15仟瓦,且可持鑛至約1〇〇〇埃之鋁 裝 .訂 本紙張尺度適用中國國家標準(CNS丨甲4規格(210X297公釐) L43335 峻濟部中央標"局Μ工消費合作社印奴 A6 B6 五、發明説明(5 ) 沈積為止。然後將晶Η轉送至第三反懕室,鋁緒合金可於 此沈積。沈積仍在低於 ΐ5〇υ進行。靶上之外施電力為 10至15仟瓦。若須要,此亦可用準直器進行。 沈積1 000埃之鋁一緒合金後,將晶片轉送至第四反應室 (或返回至第一次合金所用之反應室),鋁或不含緒之鋁 合金於其中沈積。通常,於第三反應室中,晶片之起始溫 度可為約 150t。再使用10— 15仟瓦之電力,並沈積約 1 00 0埃之鋁。當完成此初步沈積時*晶片溫度可增至約 400到500 °C, 此時最终鋁沈積發生。溫度之增加係使用 背面氣體。通常於最後沈積中,外加電力可為 5至15仟瓦 。若須要,可用300至400伏特之偏壓,但不一定需要。一 旦沈積完成,溫度可維持於450至500 °C 1至2分鐘,使鋁層 發生體擴散而平面化。使晶片冷卻並且通孔亦有效填充。 然後視須要,使晶片進一步加工。 根據本方法,沈積非常精準之鋁合金、鋁-緒及鋁合金 三層,當随後加工時,其不會沾濕通孔之表面。鋁及鋁一 结合金之多層沈積使得緒藉擴散而分布於三層中各處,因 而減少有害之球吠析出及高電阻。此種重新分布亦增加此 材料之熔點至更接近半導體工業中傳统鋁合金之熔點。 再者,使用鋁一緒合金可使通孔之起始填充溫度較低。 因緒可移入鋁層•故可避免鋁一睹合金不沾濕。隨後之 熱處理可導致鋁之體擴散或表面擴散而使鋁層充分平面化 。因此,本發明提供一種以鋁填充微米與次微米通孔及觸 點之快速、經濟、有效方法。 (請先閲讀背面之注意事項再填寫本頁) -裝 .訂 本紙張尺度適用中國國家標準(CNS)甲4規格(210X297公釐) 243535 A6 B6 五、發明説明(6 ) 佳範 最利 明專 發請 本申 對之 知加 所附 前受 目僅 者懕 明身 發本 本明 之發 明本 發, 本而 行然 執。 為述。 成闌定 已之限 此式所 模圍 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)甲4規格(210x297公釐)
Claims (1)
- A7 B743535 C7 六、申請專利範圍 1. 一種於半導體底材中填充通孔之方法,包含: 在低於1501溫度下噴鍍沈積非緒之含鋁第一層於含該 通孔之底材上; 在低於1 5 0°C溫度下噴鍍沈積一層鋁一緒合金; 噴鍍沈積非緒之含鋁第二層,其中該第二層約1〇〇〇埃厚 ,且在低於或等於150°C下沈積; 在400至500 °C之溫度下沈積非緒之含鋁第二層於該底材 上,其中所有該等層之缌厚度為約5000至約15,000埃。 2. 根據申請專利範圍第1項之方法,其中該含緒之合金包 含1至約5 SS之$者。 3. 根據申請專利範圍第1項之方法I其中該鋁一睹合金係 使用1 0 - 1 5仟瓦之外加動力,於低於1 5 0 t之溫度下沈 積者。 4. 根據申請專利範圍第1項之方法,其中該第一層為約 1000埃厚。 5. 根據申請專利範圍第 2項之方法,其中該IB之初步沈積 經由準直器進行。 6. 根據申請專利範圍第5項之方法,其中該鋁一緒合金之 沈積經由準直器進行。 7. 根據申請專利範圍第1項之方法,其中該第三層沈積1 至2分鐘時間後,使該底材維持於4 5 0 °C至5 0 0 ΐ:之溫度 (請先Μ讀背面之注意事項再璜寫本頁) .裝. 訂· A »濟邾中夹標丰局R工消費合作ii印s* 衣纸張又度適用中國國家標準(CNS)甲4规格(210 X 297公釐)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US08/018,769 US5358616A (en) | 1993-02-17 | 1993-02-17 | Filling of vias and contacts employing an aluminum-germanium alloy |
Publications (1)
Publication Number | Publication Date |
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TW243535B true TW243535B (zh) | 1995-03-21 |
Family
ID=21789696
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW083100204A TW243535B (zh) | 1993-02-17 | 1994-01-12 |
Country Status (8)
Country | Link |
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US (1) | US5358616A (zh) |
EP (1) | EP0685114A1 (zh) |
JP (1) | JPH08506935A (zh) |
KR (1) | KR960701467A (zh) |
AU (1) | AU5993994A (zh) |
CA (1) | CA2153680A1 (zh) |
TW (1) | TW243535B (zh) |
WO (1) | WO1994019826A1 (zh) |
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TW298674B (zh) * | 1995-07-07 | 1997-02-21 | At & T Corp | |
US6239029B1 (en) | 1995-07-17 | 2001-05-29 | Micron Technology, Inc. | Sacrificial germanium layer for formation of a contact |
US5644166A (en) | 1995-07-17 | 1997-07-01 | Micron Technology, Inc. | Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts |
US6238533B1 (en) * | 1995-08-07 | 2001-05-29 | Applied Materials, Inc. | Integrated PVD system for aluminum hole filling using ionized metal adhesion layer |
US5962923A (en) | 1995-08-07 | 1999-10-05 | Applied Materials, Inc. | Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches |
US5633199A (en) * | 1995-11-02 | 1997-05-27 | Motorola Inc. | Process for fabricating a metallized interconnect structure in a semiconductor device |
US5851920A (en) * | 1996-01-22 | 1998-12-22 | Motorola, Inc. | Method of fabrication of metallization system |
US5789317A (en) | 1996-04-12 | 1998-08-04 | Micron Technology, Inc. | Low temperature reflow method for filling high aspect ratio contacts |
KR100223332B1 (ko) * | 1996-06-17 | 1999-10-15 | 김영환 | 반도체 소자의 금속배선 및 그 형성방법 |
US6331482B1 (en) * | 1996-06-26 | 2001-12-18 | Micron Technology, Inc. | Method of VLSI contact, trench, and via filling using a germanium underlayer with metallization |
US5827408A (en) * | 1996-07-26 | 1998-10-27 | Applied Materials, Inc | Method and apparatus for improving the conformality of sputter deposited films |
US6309971B1 (en) | 1996-08-01 | 2001-10-30 | Cypress Semiconductor Corporation | Hot metallization process |
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GB9619461D0 (en) * | 1996-09-18 | 1996-10-30 | Electrotech Ltd | Method of processing a workpiece |
US5873983A (en) * | 1997-01-13 | 1999-02-23 | Vanguard International Semiconductor Corporation | Method for minimizing substrate to clamp sticking during thermal processing of thermally flowable layers |
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US6969448B1 (en) | 1999-12-30 | 2005-11-29 | Cypress Semiconductor Corp. | Method for forming a metallization structure in an integrated circuit |
US6455427B1 (en) | 1999-12-30 | 2002-09-24 | Cypress Semiconductor Corp. | Method for forming void-free metallization in an integrated circuit |
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KR900001825B1 (ko) * | 1984-11-14 | 1990-03-24 | 가부시끼가이샤 히다찌세이사꾸쇼 | 성막 지향성을 고려한 스퍼터링장치 |
JP2515731B2 (ja) * | 1985-10-25 | 1996-07-10 | 株式会社日立製作所 | 薄膜形成装置および薄膜形成方法 |
US4824544A (en) * | 1987-10-29 | 1989-04-25 | International Business Machines Corporation | Large area cathode lift-off sputter deposition device |
US4994162A (en) * | 1989-09-29 | 1991-02-19 | Materials Research Corporation | Planarization method |
US4970176A (en) * | 1989-09-29 | 1990-11-13 | Motorola, Inc. | Multiple step metallization process |
US5108570A (en) * | 1990-03-30 | 1992-04-28 | Applied Materials, Inc. | Multistep sputtering process for forming aluminum layer over stepped semiconductor wafer |
JP2601020B2 (ja) * | 1990-11-28 | 1997-04-16 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5171412A (en) * | 1991-08-23 | 1992-12-15 | Applied Materials, Inc. | Material deposition method for integrated circuit manufacturing |
-
1993
- 1993-02-17 US US08/018,769 patent/US5358616A/en not_active Expired - Lifetime
-
1994
- 1994-01-10 CA CA002153680A patent/CA2153680A1/en not_active Abandoned
- 1994-01-10 EP EP94906060A patent/EP0685114A1/en not_active Withdrawn
- 1994-01-10 WO PCT/US1994/000309 patent/WO1994019826A1/en not_active Application Discontinuation
- 1994-01-10 AU AU59939/94A patent/AU5993994A/en not_active Abandoned
- 1994-01-10 JP JP6518954A patent/JPH08506935A/ja active Pending
- 1994-01-10 KR KR1019950703443A patent/KR960701467A/ko not_active Application Discontinuation
- 1994-01-12 TW TW083100204A patent/TW243535B/zh active
Also Published As
Publication number | Publication date |
---|---|
CA2153680A1 (en) | 1994-09-01 |
KR960701467A (ko) | 1996-02-24 |
JPH08506935A (ja) | 1996-07-23 |
AU5993994A (en) | 1994-09-14 |
EP0685114A1 (en) | 1995-12-06 |
WO1994019826A1 (en) | 1994-09-01 |
US5358616A (en) | 1994-10-25 |
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