KR960002770A - 폴리머와 금속 사이의 공유 영역 접착 방법 및 장치 - Google Patents

폴리머와 금속 사이의 공유 영역 접착 방법 및 장치 Download PDF

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KR960002770A
KR960002770A KR1019950014559A KR19950014559A KR960002770A KR 960002770 A KR960002770 A KR 960002770A KR 1019950014559 A KR1019950014559 A KR 1019950014559A KR 19950014559 A KR19950014559 A KR 19950014559A KR 960002770 A KR960002770 A KR 960002770A
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semiconductor
metal
leadframe
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가네산 산까라나라얀안
마틴 베지 하워드
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빈센트 비. 인그라시아
모토로라 인코포레이티드
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Abstract

리드프레임(11)에 폴리머(17,19)의 접착을 개선하기 위한 리드프레임(11)과 방법에 관한 것이다. 리드프레임(11)은 상부 표면(15)과 하부 표면(18)을 가진 플래그(14)와, 리드(12)를 가진다. 미세 고정 기구(31)는 모래알형 재료로 플래그(14)를 충돌하므로서 플래그(14)의 상부 표면(15)과 하부 표면(18)내에 형성된다. 그러므로, 상부 및 하부 표면(15,18)은 거칠어진다. 반도체 다이(13)는 다이 부착 재료(17)에 의해 플러그(14)에 부착되고 반도체 다이(13)와 리드(12)의 일부분은 성형 화합물에 의해 포장된다. 피트(구멍)은 리드프레임(11)에 다이 부착 재료(17)와 성형 화합물(19)의 접착을 개선한다.

Description

폴리머와 금속 사이의 공유 영역 접착 방법 및 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예를 따라서 거칠게한 반도체 리드프레임에 장착된 반도체 다이의 단면도,
제2도는 제1도의 반도체 리드프레임의 일부분의 확대도.

Claims (5)

  1. 폴리머(17,19)와 금속 표면 또는 금속 합금 표면중 하나(15,18)사이의 공유영역 접착을 개선하기 위한 방법에 있어서, 금속 표면 또는 금속 합금 표면중 하나(15,18)을 제공하는 단계와, 상기 금속 표면 또는 금속 합금 표면중 하나(15,18)를 가스 운반 매체내에 현수된 모래알형 재료로 충돌시키는 단계와, 상기 금속 표면또는 금속 합금 표면중 하나(15,18)의 일부분을 성형 화합물(19)로 포장되는 단계를 포함하는 것을 특징으로 하는 공유영역 접착 방법.
  2. 제1항에 있어서, 상기 금속 표면 또는 합금 표면 중 하나(15,18)를 모래알형 재료로 충돌시키는 단계는 상기 금속 표면 또는 합금 표면중 하나(15,18)를 모래알형 재료로 타격하는 단계를 부가로 포함하는 것을 특징으로 하는 공유영역 접착 방법.
  3. 폴리머(17,19)와 반도체 리드프레임(11)사이의 공유영역 접착을 개선하기 위한 방법에 있어서, 상기 반도체 리드프레임(11)을 제공하는 단계와, 상기 반도체 리드프레임(11)의 일부분을 가스 매체를 통해 모래알형 재료를 사용하여 거칠게하는 단계와, 상기 반도체 리드프레임(11)에 적어도 하나의 반도체 다이(13)를 장착하는 단계와, 상기 적어도 하나의 반도체 다이(13)의 반도체 리드프레임(11)을 폴리머(19)내로 포장하는 단계를 포함하는 것을 특징으로 하는 공유영역 접착 방법.
  4. 제3항에 있어서, 상기 반도체 리드프레임(11)의 일부분을 거칠게하는 단계는 모래, 이산화실리콘, 산화알루미늄, 탄화실리콘과 중탄산염으로 구성된 그룹으로부터 선택된 모래알형 재료를 사용하여 반도체 리드프레임(11)의 일부분을 거칠게하는 단계를 부가로 포함하는 것을 특징으로 하는 공유영역 접착 방법.
  5. 일부분이 미세 고정 기구(31)와 적어도 1,500옹스트롬의 표면 조도를 가지는 제1표면(15)과 제2표면(18)을 가지는 반도체 리드프레임(11)과, 상기 제1표면(15)에 장착된 반도체 다이(13)와, 상기 반도체 다이(13)와 미세 고정 기구(31)를 가진 제1표면(15)을 포장하는 성형 화합물(19)을 포함하는 것을 특징으로 하는 반도체 패키지(10).
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950014559A 1994-06-06 1995-06-02 폴리머와 금속 사이의 공유 영역 접착 방법 및 장치 KR960002770A (ko)

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US08/254,842 US5554569A (en) 1994-06-06 1994-06-06 Method and apparatus for improving interfacial adhesion between a polymer and a metal
US254,842 1994-06-06

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Publication number Priority date Publication date Assignee Title
JP3534347B2 (ja) * 1993-11-04 2004-06-07 日東電工株式会社 半導体素子の製造方法,ウエハ貼付用粘着シート
JP3417079B2 (ja) * 1994-08-31 2003-06-16 ソニー株式会社 半導体装置の製造方法
US5834687A (en) * 1995-06-07 1998-11-10 Acuson Corporation Coupling of acoustic window and lens for medical ultrasound transducers
JP3345878B2 (ja) * 1997-02-17 2002-11-18 株式会社デンソー 電子回路装置の製造方法
US8172897B2 (en) 1997-04-15 2012-05-08 Advanced Cardiovascular Systems, Inc. Polymer and metal composite implantable medical devices
US10028851B2 (en) 1997-04-15 2018-07-24 Advanced Cardiovascular Systems, Inc. Coatings for controlling erosion of a substrate of an implantable medical device
US6240616B1 (en) 1997-04-15 2001-06-05 Advanced Cardiovascular Systems, Inc. Method of manufacturing a medicated porous metal prosthesis
US20030011048A1 (en) * 1999-03-19 2003-01-16 Abbott Donald C. Semiconductor circuit assembly having a plated leadframe including gold selectively covering areas to be soldered
US6274927B1 (en) 1999-06-03 2001-08-14 Amkor Technology, Inc. Plastic package for an optical integrated circuit device and method of making
US7807211B2 (en) 1999-09-03 2010-10-05 Advanced Cardiovascular Systems, Inc. Thermal treatment of an implantable medical device
US6388336B1 (en) * 1999-09-15 2002-05-14 Texas Instruments Incorporated Multichip semiconductor assembly
US6245597B1 (en) * 1999-09-28 2001-06-12 Microchip Technology Incorporated Method for reducing die cracking in integrated circuits
US6720642B1 (en) * 1999-12-16 2004-04-13 Fairchild Semiconductor Corporation Flip chip in leaded molded package and method of manufacture thereof
US6184064B1 (en) * 2000-01-12 2001-02-06 Micron Technology, Inc. Semiconductor die back side surface and method of fabrication
US6399182B1 (en) 2000-04-12 2002-06-04 Cmc Wireless Components, Inc. Die attachment utilizing grooved surfaces
JP3602453B2 (ja) * 2000-08-31 2004-12-15 Necエレクトロニクス株式会社 半導体装置
US6805898B1 (en) 2000-09-28 2004-10-19 Advanced Cardiovascular Systems, Inc. Surface features of an implantable medical device
US6913617B1 (en) 2000-12-27 2005-07-05 Advanced Cardiovascular Systems, Inc. Method for creating a textured surface on an implantable medical device
US6861720B1 (en) 2001-08-29 2005-03-01 Amkor Technology, Inc. Placement template and method for placing optical dies
US6784534B1 (en) 2002-02-06 2004-08-31 Amkor Technology, Inc. Thin integrated circuit package having an optically transparent window
DE10221503A1 (de) 2002-05-14 2003-11-27 Infineon Technologies Ag Zur wenigstens teilweisen Beschichtung mit einer Substanz bestimmter Metallgegenstand
US6879050B2 (en) * 2003-02-11 2005-04-12 Micron Technology, Inc. Packaged microelectronic devices and methods for packaging microelectronic devices
JP3841768B2 (ja) * 2003-05-22 2006-11-01 新光電気工業株式会社 パッケージ部品及び半導体パッケージ
US20050118344A1 (en) 2003-12-01 2005-06-02 Pacetti Stephen D. Temperature controlled crimping
DE10348715B4 (de) * 2003-10-16 2006-05-04 Infineon Technologies Ag Verfahren zum Herstellen eines Flachleiterrahmens mit verbesserter Haftung zwischen diesem und Kunststoff sowie Flachleiterrahmen
WO2005071741A2 (de) * 2004-01-27 2005-08-04 Infineon Technologies Ag Haftvermittelnde organische beschichtungen in halbleitergehäusen
DE102004047510A1 (de) * 2004-09-28 2006-04-13 Infineon Technologies Ag Halbleiterbauteil mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten
DE102005020453B4 (de) * 2005-04-29 2009-07-02 Infineon Technologies Ag Halbleiterbauteil mit einer Flachleiterstruktur und Verfahren zur Herstellung einer Flachleiterstruktur und Verfahren zur Herstellung eines Halbleiterbauteils
TWI275149B (en) * 2005-05-09 2007-03-01 Phoenix Prec Technology Corp Surface roughing method for embedded semiconductor chip structure
DE102005028704B4 (de) * 2005-06-20 2016-09-08 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauteils mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten
TWI273636B (en) 2005-08-02 2007-02-11 Chipmos Technologies Inc Chip package having asymmetric molding
CN100437989C (zh) * 2005-08-05 2008-11-26 南茂科技股份有限公司 不对称铸模的芯片封装体
DE102005047856B4 (de) * 2005-10-05 2007-09-06 Infineon Technologies Ag Halbleiterbauteil mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten, Systemträger zur Aufnahme der Halbleiterbauteilkomponenten und Verfahren zur Herstellung des Systemträgers und von Halbleiterbauteilen
DE102005061248B4 (de) 2005-12-20 2007-09-20 Infineon Technologies Ag Systemträger mit in Kunststoffmasse einzubettenden Oberflächen, Verfahren zur Herstellung eines Systemträgers und Verwendung einer Schicht als Haftvermittlerschicht
DE102006022254B4 (de) * 2006-05-11 2008-12-11 Infineon Technologies Ag Halbleiterbauteil mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten, Anordnung für eine Mehrzahl von Halbleiterbauteilen und Verfahren zur Herstellung von Halbleiterbauteilen
DE102006059526B4 (de) * 2006-12-14 2008-09-25 Infineon Technologies Ag Halbleiterbauteil, Nutzen mit in Zeilen und Spalten angeordneten Halbleiterbauteilen und Verfahren zur Herstellung eines Halbleiterbauteils
US8450148B2 (en) 2006-12-14 2013-05-28 Infineon Technologies, Ag Molding compound adhesion for map-molded flip-chip
CN100464416C (zh) * 2007-04-29 2009-02-25 江苏长电科技股份有限公司 防止半导体塑料封装体内元器件分层的封装方法
CN100466245C (zh) * 2007-04-29 2009-03-04 江苏长电科技股份有限公司 有效改善半导体塑料封装体内元器件分层的封装方法
CN100470785C (zh) * 2007-04-29 2009-03-18 江苏长电科技股份有限公司 改善半导体塑料封装体内元器件分层的有效封装方法
CN100483705C (zh) * 2007-04-29 2009-04-29 江苏长电科技股份有限公司 可以防止半导体塑料封装体内元器件分层的封装方法
US20090315159A1 (en) * 2008-06-20 2009-12-24 Donald Charles Abbott Leadframes having both enhanced-adhesion and smooth surfaces and methods to form the same
CN101683757A (zh) * 2008-09-25 2010-03-31 比亚迪股份有限公司 一种成型方法及其产品
US8124447B2 (en) * 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
DE102011083791A1 (de) * 2011-09-29 2013-04-04 Robert Bosch Gmbh Verfahren zur Herstellung einer Lötverbindung
US8956920B2 (en) * 2012-06-01 2015-02-17 Nxp B.V. Leadframe for integrated circuit die packaging in a molded package and a method for preparing such a leadframe
US8822274B2 (en) * 2012-10-04 2014-09-02 Texas Instruments Incorporated Packaged IC having printed dielectric adhesive on die pad
CN103021974B (zh) * 2013-01-06 2015-05-06 日月光半导体制造股份有限公司 半导体封装件
JP2014203861A (ja) * 2013-04-02 2014-10-27 三菱電機株式会社 半導体装置および半導体モジュール
US9685351B2 (en) 2014-07-18 2017-06-20 Nxp Usa, Inc. Wire bond mold lock method and structure
CN106634643A (zh) * 2015-11-03 2017-05-10 株洲时代新材料科技股份有限公司 一种提高金属与硅橡胶粘接性能的表面处理方法
DE102016117841A1 (de) 2016-09-21 2018-03-22 HYUNDAI Motor Company 231 Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung
JP6479265B2 (ja) * 2016-12-27 2019-03-06 古河電気工業株式会社 リードフレーム材およびその製造方法ならびに半導体パッケージ
CN111180109B (zh) * 2018-11-12 2021-06-25 昇印光电(昆山)股份有限公司 导电膜及制备方法
CN112563144B (zh) * 2020-12-24 2022-09-30 新恒汇电子股份有限公司 一种引线框架表面处理工艺
WO2023140042A1 (ja) * 2022-01-20 2023-07-27 ローム株式会社 半導体装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2244771A (en) * 1938-08-16 1941-06-10 Int Standard Electric Corp Composite conductor and contact between conductors
JPS6139556A (ja) * 1984-07-31 1986-02-25 Toshiba Corp リ−ドフレ−ム
JPS61119653A (ja) * 1984-11-15 1986-06-06 Hitachi Metals Ltd Icリ−ドフレ−ム材料
JPS6236676A (ja) * 1985-08-10 1987-02-17 Canon Inc 光導電部材用の支持体及び該支持体を有する光導電部材
US5147822A (en) * 1988-08-26 1992-09-15 Semiconductor Energy Laboratory Co., Ltd. Plasma processing method for improving a package of a semiconductor device
US5205036A (en) * 1988-10-17 1993-04-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device with selective coating on lead frame
US5164815A (en) * 1989-12-22 1992-11-17 Texas Instruments Incorporated Integrated circuit device and method to prevent cracking during surface mount
US5197234A (en) * 1990-02-27 1993-03-30 Gillenwater R Lee Abrasive engraving process
JPH0454501A (ja) * 1990-05-23 1992-02-21 Matsushita Electric Ind Co Ltd 制御装置
US5227661A (en) * 1990-09-24 1993-07-13 Texas Instruments Incorporated Integrated circuit device having an aminopropyltriethoxysilane coating
JP2541357B2 (ja) * 1990-10-29 1996-10-09 日本電気株式会社 チップ型固体電解コンデンサの製造方法
KR940006083B1 (ko) * 1991-09-11 1994-07-06 금성일렉트론 주식회사 Loc 패키지 및 그 제조방법
US5533922A (en) * 1993-03-22 1996-07-09 Eikichi Yamaharu Method and apparatus for pretreating electronic component manufacturing frame

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