CN100466245C - 有效改善半导体塑料封装体内元器件分层的封装方法 - Google Patents

有效改善半导体塑料封装体内元器件分层的封装方法 Download PDF

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CN100466245C
CN100466245C CNB2007100223461A CN200710022346A CN100466245C CN 100466245 C CN100466245 C CN 100466245C CN B2007100223461 A CNB2007100223461 A CN B2007100223461A CN 200710022346 A CN200710022346 A CN 200710022346A CN 100466245 C CN100466245 C CN 100466245C
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die
attach area
semiconductor plastic
molding compound
epoxy molding
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CN101075598A (zh
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梁志忠
王新潮
于燮康
茅礼卿
潘明东
陶玉娟
闻荣福
周正伟
李福寿
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Changdian Technology Management Co ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明涉及一种有效改善半导体塑料封装体内元器件分层的封装方法，属半导体封装技术领域。其特征在于：在半导体塑料封装体内，在金属引线框(1)上制作出可使环氧树脂塑封料贯穿用的锚孔(3)，同时在与环氧树脂塑封料(2)结合的金属引线框(1)的表面局部镀上金属层(4)。本发明半导体塑料封装元器件分层问题的改善，有利于提高元器件的散热能力和抗热应力变化能力，产品的密封性、功能参数以及可靠性都得到了很好的保证。

Description

有效改善半导体塑料封装体内元器件分层的封装方法
技术领域：
本发明涉及一种半导体塑料封装体元器件，尤其是涉及一种有效改善半导体塑料封装体内元器件分层的封装方法。属半导体封装技术领域。
背景技术：
半导体塑料封装元器件基本采用多种物质相结合的封装体，其中的材料主要有金属引线框、环氧树脂、金属丝、高分子粘合剂、金属镀层等。但是，不同的物质会因温度、湿度、振动等因素的变化而容易造成在不同物质之间产生分层；尤其是在高温环境中，由于不同物质的热膨胀系数是不一样的，所以会在水平方向或垂直方向产生不同程度的拉、推应力，进而在不同物质间产生分层(如图6(a)、7(a)、8(a)、9(a)所示)，最终导致半导体塑料封装元器件的功能缺陷或早期失效等问题。
发明内容：
本发明的目的在于克服上述不足，提供一种有效改善半导体塑料封装体内元器件分层的封装方法。
本发明的目的可以通过以下二个方案加以实现：
方案一：
在半导体塑料封装体内，在金属引线框上制作出可使环氧树脂塑封料贯穿用的锚孔，同时在与环氧树脂塑封料结合的金属引线框的表面局部镀上金属层。锚孔的制作可以采用机械或蚀刻加工或刮除等方式来实现。局部镀金属可采用电镀、沉积、蒸金、溅镀等方式来实现。锚孔可降低二者在垂直(Z轴)方向上的应力，从而是二者在垂直(Z轴)方向上锁紧(如图4)。同时，在金属引线框的表面通过局部镀金属层的方式来相对增加引线框金属底材的表面积：一方面可以减少金属引线框与环氧树脂间的介质；另一方面，金属底材一般采用铜材，而金属镀层往往采用金、银等，因为铜与环氧树脂的粘合力要大大优于金和银，所以局部镀金属层的方法也间接增加了金属引线框与环氧树脂间的粘合力(如图5)。因此，以上二种方案的结合使用可以使金属引线框与环氧树脂之间相互咬得更紧，从而起到防止或减少分层的作用。
方案二：
方案二是在方案一的基础上，在与环氧树脂塑封料结合的金属引线框的表面制作粗糙面。其制作可采用机械或蚀刻加工或刮除等方式来实现。通过在金属引线框的表层制作粗糙面来增加与环氧树脂间的结合面积，减少因拉力等因素造成的金属引线框与环氧树脂之间的滑动力(如图6)。因此，以上三种方案的结合使用可以使金属引线框与环氧树脂之间相互咬得更紧，从而起到防止或减少分层的作用。
本发明半导体塑料封装元器件分层问题的改善，有利于提高元器件的散热能力和抗热应力变化能力，产品的密封性、功能参数以及可靠性都得到了很好的保证。
附图说明
图1为本发明的实施例1示意图。
图2为本发明的实施例2示意图。
图3为本发明的典型完整塑封体结构示意图。
图4(a)、(b)为制作锚孔前后金属引线框与环氧树脂塑封料接合面的受力对比图。
图5(a)、(b)为镀局部金属层前后金属引线框与环氧树脂塑封料接合面的受力对比图。
图6(a)、(b)为制作粗糙面前后金属引线框与环氧树脂塑封料接合面的受力对比图。
图中：金属引线框1，环氧树脂塑封料2，锚孔3，金属层4，粗糙面5，金属丝6，硅材芯片7。
具体实施方式：
实施例1：
参见图1，本发明有效改善半导体塑料封装体内元器件分层的封装方法，在半导体塑料封装体内，在金属引线框1上制作出可使环氧树脂塑封料贯穿用的锚孔3，同时在与环氧树脂塑封料2结合的金属引线框1的表面局部镀上金属层4。
实施例2：
参见图2，实施例2是在实施例1的基础上，在与环氧树脂塑封料2结合的金属引线框1的表面制作粗糙面5。
参见图3，图3为典型完整塑封体结构示意图。
参见图4、5、6，图4、5、6为本发明改善前后金属引线框与环氧树脂塑封料接合面的受力对比图。

Claims (2)

1、一种有效改善半导体塑料封装体内元器件分层的封装方法，其特征在于：在半导体塑料封装体内，在金属引线框(1)上制作出可使环氧树脂塑封料贯穿用的锚孔(3)，同时在与环氧树脂塑封料(2)结合的金属引线框(1)的表面局部镀上金属层(4)，在与环氧树脂塑封料(2)结合的金属引线框(1)的表面制作粗糙面(5)，所述的锚孔(3)的制作是采用机械或蚀刻加工方式来实现，局部镀金属层(4)的制作是采用沉积方式来实现，所述的粗糙面(5)的制作是采用机械或蚀刻加工方式来实现。
2、根据权利要求1所述的一种有效改善半导体塑料封装体内元器件分层的封装方法，其特征在于：所述沉积是电镀或蒸金或溅镀。
CNB2007100223461A 2007-04-29 2007-04-29 有效改善半导体塑料封装体内元器件分层的封装方法 Active CN100466245C (zh)

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CN103050468A (zh) * 2012-12-17 2013-04-17 华天科技（西安）有限公司 一种带有梯形孔的冲压框架的扁平多芯片封装件
CN112133640B (zh) * 2020-11-24 2021-02-09 宁波康强电子股份有限公司 一种具有粗糙侧壁的引线框架的制备方法

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Publication number Priority date Publication date Assignee Title
CN1116770A (zh) * 1994-06-06 1996-02-14 摩托罗拉公司 用来改善聚合物同金属间界面粘合性的方法和设备
US6184064B1 (en) * 2000-01-12 2001-02-06 Micron Technology, Inc. Semiconductor die back side surface and method of fabrication
CN1848420A (zh) * 2005-04-15 2006-10-18 三星Techwin株式会社 用于半导体封装的引线框
CN1851914A (zh) * 2006-05-29 2006-10-25 朱冬生 一种引线框架以及具有所述引线框架的半导体器件
CN2893922Y (zh) * 2006-04-19 2007-04-25 宁波康强电子股份有限公司 改进型大功率引线框架
CN201038151Y (zh) * 2007-04-29 2008-03-19 江苏长电科技股份有限公司 有效改善半导体塑料封装体内元器件分层的封装方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1116770A (zh) * 1994-06-06 1996-02-14 摩托罗拉公司 用来改善聚合物同金属间界面粘合性的方法和设备
US6184064B1 (en) * 2000-01-12 2001-02-06 Micron Technology, Inc. Semiconductor die back side surface and method of fabrication
CN1848420A (zh) * 2005-04-15 2006-10-18 三星Techwin株式会社 用于半导体封装的引线框
CN2893922Y (zh) * 2006-04-19 2007-04-25 宁波康强电子股份有限公司 改进型大功率引线框架
CN1851914A (zh) * 2006-05-29 2006-10-25 朱冬生 一种引线框架以及具有所述引线框架的半导体器件
CN201038151Y (zh) * 2007-04-29 2008-03-19 江苏长电科技股份有限公司 有效改善半导体塑料封装体内元器件分层的封装方法

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