CN201478293U - 芯片倒扣焊封装的气密密封结构 - Google Patents

芯片倒扣焊封装的气密密封结构 Download PDF

Info

Publication number
CN201478293U
CN201478293U CN2009202304152U CN200920230415U CN201478293U CN 201478293 U CN201478293 U CN 201478293U CN 2009202304152 U CN2009202304152 U CN 2009202304152U CN 200920230415 U CN200920230415 U CN 200920230415U CN 201478293 U CN201478293 U CN 201478293U
Authority
CN
China
Prior art keywords
chip
layer
metal layer
base board
seal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2009202304152U
Other languages
English (en)
Inventor
丁荣峥
蒋长顺
唐桃扣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Zhongwei High-tech Electronics Co., Ltd.
CETC 58 Research Institute
Original Assignee
WUXI ZHONGWEI HIGH-TECH ELECTRONICS Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by WUXI ZHONGWEI HIGH-TECH ELECTRONICS Co Ltd filed Critical WUXI ZHONGWEI HIGH-TECH ELECTRONICS Co Ltd
Priority to CN2009202304152U priority Critical patent/CN201478293U/zh
Application granted granted Critical
Publication of CN201478293U publication Critical patent/CN201478293U/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本实用新型涉及到一种芯片倒扣焊封装的气密密封结构,其包括安装基板与芯片,芯片通过焊接层固定在安装基板上表面,在安装基板与芯片之间对应焊接层外侧设有填充树脂层,在芯片外侧的安装基板上表面粘结有密封金属层,所述密封金属层为首尾相接的环状片材,密封金属层内圈侧壁与芯片侧壁之间存在间隙,在密封金属层与芯片上镀有覆盖金属层,所述覆盖金属层嵌入密封金属层与芯片之间的间隙并与安装基板接触。本实用新型提高了导热性能,产品的可靠性,覆盖金属层与基板形成了一个全密封整体,解决了FC倒口焊封装电路“爆米花”、侵蚀等的质量问题,提高产品使用的适应恶劣环境的能力;增强了封装结构强度,提高了封装产品的可靠性。

Description

芯片倒扣焊封装的气密密封结构
技术领域
本实用新型涉及到一种芯片倒扣焊封装(FC)的气密密封结构,属于微电子封装技术领域。
背景技术
为满足不同应用和性能需求,制造好的IC等芯片需要采用不同的封装形式。目前广泛应用的一种芯片封装技术是把芯片通过倒装工艺装到基板上,然后对底部进行下填充完成封装,或芯片粘结到基板上通过引线键合连接,用环氧树脂材料对芯片进行包封保护,但这种封装是非气密性的,空气中水汽、树脂中的离子等透过树脂分子间隙向芯片扩散,随时间、温度等外界应力作用下,对芯片铝压点甚至布线产生腐蚀而造成电性能及可靠性下降。要达到气密封装要求,常采用的措施是在芯片外围焊接一个空腔型金属帽,有人据此结构申请了名为“微电子电路的空腔型封装方法”(专利号:1445831A)的发明专利。当盖板体积较大时,这种带有金属帽的封装结构封口周长也会增加,对于长周长封口环封装,其气密性成品率低,且金属帽显著地增大封装的体积和重量,更不利于器件的散热,在高性能系统中,基板上空间是极其有限的,因此,这不能满足小型化、轻便化和高密度、高可靠封装的要求,从而增加系统的总重量和体积。
发明内容
本实用新型的目的是克服现有技术中存在的不足,提供一种可减小封装体积和降低封装重量、增加封装的导热性、提高封装密度并能有效提高封装成品率的芯片倒扣焊封装的气密密封结构。
按照本实用新型提供的技术方案,所述芯片倒扣焊封装的气密密封结构,
包括安装基板与芯片,特征是:芯片通过互连焊接层固定在安装基板上表面,在安装基板与芯片之间对应互连焊接层外侧设有填充树脂层,在芯片外侧的安装基板上表面粘结有密封金属层,密封金属层内圈侧壁与芯片侧壁之间设有间隙,在密封金属层与芯片上镀有覆盖金属层。
所述密封金属层为首尾相接的环状片材。
所述覆盖金属层将芯片有源区、互连焊接层、填充树脂层形成一个气密性的密封。
本实用新型从非密封变为密封,基本不增加器件的封装体积和重量;本新型是在芯片包封材料表面直接镀覆盖金属层,可以根据可靠性寿命要求调整覆盖金属层,但其尺寸是非常小的,基本上不会额外增加封装体积,封装重量增加也非常小,不影响系统的组装。本实用新型提高了导热性能,产品的可靠性,覆盖金属层与基板形成了一个全密封整体,解决了FC倒口焊封装电路“爆米花”、侵蚀等的质量问题,提高产品使用的适应恶劣环境的能力;增强了封装结构强度,提高了封装产品的可靠性,且可以满足不同尺寸芯片的封装,适用范围广。
附图说明
图1是本实用新型的整体结构示意图。
图2是图1的俯视图。
具体实施方式
下面结合具体附图和实施例对本实用新型作进一步说明。
如图所示,本实用新型主要由安装基板1、芯片2、填充树脂层3、覆盖金属层4、密封金属层5及互连焊接层6等构成。
该芯片倒扣焊封装的气密密封结构,包括安装基板1与芯片2,芯片2通过填充树脂层3、互连焊接层6固定在安装基板1上表面,在芯片2外侧的安装基板1上表面粘结有密封金属层5,所述密封金属层5为首尾相接的环状片材,密封金属层5内圈侧壁与芯片2侧壁之间存在间隙,在密封金属层5与芯片2上镀有覆盖金属层4,所述覆盖金属层4嵌入密封金属层5与芯片2之间的间隙并与密封金属层5、芯片2接触。
本实用新型中芯片2通过倒装芯片技术由互连焊接层6固定到安装基板1上,再利用环氧树脂的填充树脂层3对芯片2进行底部填充来保护芯片2,提高机械强度、释放芯片2与安装基板1间的热应力,之后用覆盖金属层4进行密封。在进行金属密封前需对覆盖金属层4表面进行粗化处理、活化处理以增强覆盖金属层4与安装基板1的结合力强度。覆盖金属层4可以采用通过蒸发或溅射等方法来实现多层金属层的沉积,最外层可以采用喷锡、电镀等方式进行快速、高效增厚工艺处理。覆盖金属层4按需要密封的区域图形确定,覆盖金属层4与安装基板1和安装基板1上的密封金属层5构成全密封区域,芯片2的有源区、互连等与外界隔离,实现对芯片气密性封装的目的。

Claims (3)

1.一种芯片倒扣焊封装的气密密封结构,包括安装基板(1)与芯片(2),其特征是:芯片(2)通过互连焊接层(6)固定在安装基板(1)上表面,在安装基板(1)与芯片(2)之间对应互连焊接层(6)外侧设有填充树脂层(3),在芯片(2)外侧的安装基板(1)上表面粘结有密封金属层(5),密封金属层(5)内圈侧壁与芯片(2)侧壁之间设有间隙,在密封金属层(5)与芯片(2)上镀有覆盖金属层(4)。
2.如权利要求1所述的芯片倒扣焊封装的气密密封结构,其特征在于所述密封金属层(5)为首尾相接的环状片材。
3.如权利要求1所述的芯片倒扣焊封装的气密密封结构,其特征在于所述覆盖金属层(4)将芯片(2)有源区、互连焊接层(6)、填充树脂层(3)形成一个气密性的密封。
CN2009202304152U 2009-08-20 2009-08-20 芯片倒扣焊封装的气密密封结构 Expired - Lifetime CN201478293U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2009202304152U CN201478293U (zh) 2009-08-20 2009-08-20 芯片倒扣焊封装的气密密封结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2009202304152U CN201478293U (zh) 2009-08-20 2009-08-20 芯片倒扣焊封装的气密密封结构

Publications (1)

Publication Number Publication Date
CN201478293U true CN201478293U (zh) 2010-05-19

Family

ID=42414553

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009202304152U Expired - Lifetime CN201478293U (zh) 2009-08-20 2009-08-20 芯片倒扣焊封装的气密密封结构

Country Status (1)

Country Link
CN (1) CN201478293U (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102749167A (zh) * 2012-06-20 2012-10-24 北京大学 一种含有硅通孔的压力传感器封装结构
CN103021887A (zh) * 2012-12-31 2013-04-03 无锡中微高科电子有限公司 有散热要求fc电路的气密性封帽方法
CN113049171A (zh) * 2019-12-27 2021-06-29 霍尼韦尔国际公司 无引线压力传感器

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102749167A (zh) * 2012-06-20 2012-10-24 北京大学 一种含有硅通孔的压力传感器封装结构
CN102749167B (zh) * 2012-06-20 2014-11-05 北京大学 一种含有硅通孔的压力传感器封装结构
CN103021887A (zh) * 2012-12-31 2013-04-03 无锡中微高科电子有限公司 有散热要求fc电路的气密性封帽方法
CN103021887B (zh) * 2012-12-31 2015-04-22 无锡中微高科电子有限公司 有散热要求fc电路的气密性封帽方法
CN113049171A (zh) * 2019-12-27 2021-06-29 霍尼韦尔国际公司 无引线压力传感器
US11867583B2 (en) 2019-12-27 2024-01-09 Honeywell International Inc. Leadless pressure sensors

Similar Documents

Publication Publication Date Title
CN202772854U (zh) 芯片级封装声表面波器件
US20120091487A1 (en) Light emitting diode package and method for manufacturing the same
CN103456645B (zh) 先蚀后封三维系统级芯片正装堆叠封装结构及工艺方法
US20080166000A1 (en) Packaging structure and method of a mems microphone
CN212571036U (zh) 一种深紫外led的封装支架和封装结构
US9378986B2 (en) Method for mounting a chip and chip package
TW201445780A (zh) 發光二極體封裝結構
CN201478293U (zh) 芯片倒扣焊封装的气密密封结构
CN100470785C (zh) 改善半导体塑料封装体内元器件分层的有效封装方法
CN103928409B (zh) 一种集成电路倒扣焊气密性封装结构
CN102856468A (zh) 发光二极管封装结构及其制造方法
CN103618041A (zh) 一种esd保护的led封装结构及其封装方法
CN101471307A (zh) 半导体封装体及其制造方法
CN102593068B (zh) 斜锥状凸块结构
CN109713092A (zh) Uv led的封装结构及uv led的封装方法
CN103730426A (zh) 气腔式封装结构及方法
TWI414092B (zh) 發光二極體封裝結構及其製造方法
CN100464416C (zh) 防止半导体塑料封装体内元器件分层的封装方法
CN103346234A (zh) 一种led封装结构及其封装方法
CN201466017U (zh) 超小型微电子电路的平面型载体空腔气密性封装结构
CN101958252B (zh) 超小型微电子电路的平面型载体空腔气密性封装方法
CN201048129Y (zh) 改善半导体塑料封装体内元器件分层的有效封装方法
CN105580130A (zh) 用于安装芯片的衬底和芯片封装
CN212257396U (zh) 一种双面传感器封装结构及传感器
CN205160485U (zh) 一种声表面波滤波器封装结构

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO.

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20110729

Address after: 214028 B building, international science and technology cooperation Park, 2 Taishan Road, Wuxi Economic Development Zone, Wuxi New District, Jiangsu,, China

Co-patentee after: China Electronics Technology Group Corporation No.58 Research Institute

Patentee after: Wuxi Zhongwei High-tech Electronics Co., Ltd.

Address before: 214028 B building, international science and technology cooperation Park, 2 Taishan Road, Wuxi Economic Development Zone, Wuxi New District, Jiangsu,, China

Patentee before: Wuxi Zhongwei High-tech Electronics Co., Ltd.

CX01 Expiry of patent term

Granted publication date: 20100519

CX01 Expiry of patent term