KR930020584A - 반도체 장치 제조방법 - Google Patents

반도체 장치 제조방법 Download PDF

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Publication number
KR930020584A
KR930020584A KR1019930002987A KR930002987A KR930020584A KR 930020584 A KR930020584 A KR 930020584A KR 1019930002987 A KR1019930002987 A KR 1019930002987A KR 930002987 A KR930002987 A KR 930002987A KR 930020584 A KR930020584 A KR 930020584A
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KR
South Korea
Prior art keywords
metal
dielectric material
sidewall spacers
etching
line
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KR1019930002987A
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English (en)
Inventor
에스.로스 스코트
씨. 커쉬 하워드
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빈센트 비.인그라시아
모토로라 인코포레이티드
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Application filed by 빈센트 비.인그라시아, 모토로라 인코포레이티드 filed Critical 빈센트 비.인그라시아
Publication of KR930020584A publication Critical patent/KR930020584A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

반도체 장치(20)는 도통 랜딩 패드를 사용하지 않고도 제1금속선 및 그위에 놓인 제2금속선(24)간에 접촉을 만든다. 측벽 스페이서(30)는 금속선(22)의 양 측면에 인접하여 형성되어, 위에 놓인 유전제층(30)내에서 개구(34)를 형성하는 동안, 측벽 스페이서는 개구가 오정렬된 경우에 밑에 놓인 유전제층의 트랜칭을 방지한다. 측벽 스페이서는 유전체층(32)의 에칭 속도보다 상당히 높은 에칭 속도를 갖는 유전체 물질로 형성된다. 또 다른 실시예에서, 측벽 스페이서의 부분은 제2금속층(42)을 증착하기 앞서 선택적으로 제거된다. 제2금속층을 증착하자마자 금속선(22)의 측면은 제2금속과 국부적으로 클래드되어, 접촉 면적을 증가시키고 접촉 저항을 낮게한다.

Description

반도체 장치 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명을 따르는 반도체 장치의 평면도.
제5도는 선 5-5을 따라서 잘라서 본 제4도의 반도체장치를 도시한 단면도.

Claims (3)

  1. 반도체 기판(26)을 제공하는 단계와, 상기 기판위에 놓이고 양측면을 갖는 제1금속 물질로 이루어진 제1상호접속선(22)을 형성하는 단계와, 상기 제1상호접속선의 한측면에 인접하고 제1에칭 속도를 갖는 제1유전체 물질(30 또는 62)을 형성하는 단계와, 상기 제1유전체 및 물질 상기 제1상호접속선 위에 놓이고 상기 제1에칭 속도보다 실질적으로 빠른 제2에칭 속도서를 갖는 제2유전체 물질(32)을 형성하는 단계와, 상기 일부 제1상호접속선위에 놓이는 개구(34 및 66)를 형성하도록 제2유전체 물질의 일부를 제거하는 단계로서, 여기서 상기 제2유전체물질이 상기 제1유전체 물질에 대해 선택적으로 제거되는 상기 제거 단계와, 상기 제1금속 상호접속선에 접촉을 형성하도록 상기 개구를 채우는 제2금속물질(22,42 또는 68)을 증착하는 상기 단계를 구비하는 반도체 장치(20,40 또는 60)제조방법.
  2. 제1항에 있어서, 상기 개구 밑의 영역에서 상기 제1유전체 물질을 상기 제1상호접속선의 측면으로부터 제거하는 단계와, 접촉 형성동안, 상기 제1의 유전체 물질이 제거되는 상기 제1상호접속선의 측면을 상기 제2금속물질과 클래드하는 단계를 더 구비하는 반도체장치(20,40, 또는 60)제조방법.
  3. 반도체 기판(26)을 제공하는 단계와, 상기 반도체 기판위에 놓이고 윗면과 양측면을 갖는 금속선(22)을 형성하는 단계와, 상기 금속선의 양측면에 인접하고 제1에칭 속도를 갖는 제1유전체 물질로 이루어진 측벽 스페이서(30)를 형성하는 단계와, 상기 금속선 및 측벽 스페이서에 걸쳐 제2유전체 물질(32)을 증착시키는 단계로서, 상기 제2유전체 물질이 상기 제1에칭 속도보다 실질적으로 더 빠른 제2에칭 속도를 갖는 증착 단계와, 상기 측벽 스페이서를 넘어서 확장됨이 없이 상기 금속선의 적어도 일부 위에 놓이는 개구(34)를 상기 제2유전체 물질에 에칭하는 단계로서, 상기 제2유전체 물질이 측벽 스페이서를 실질적으로 에칭함이 없이 에칭하는 상기 에칭 단계와, 접촉을 상기 금속선에 형성하도록 상기 개구를 금속물질(24)로 채우는 단계를 구비하는 반도체 장치(20) 제조방법
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930002987A 1992-03-02 1993-02-27 반도체 장치 제조방법 KR930020584A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US844,044 1992-03-02
US07/844,044 US5286674A (en) 1992-03-02 1992-03-02 Method for forming a via structure and semiconductor device having the same

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US5286674A (en) 1994-02-15
JPH0645452A (ja) 1994-02-18

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