KR930010987A - 다이나믹형 ram의 특수 모드제어방법 - Google Patents

다이나믹형 ram의 특수 모드제어방법 Download PDF

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Publication number
KR930010987A
KR930010987A KR1019920020963A KR920020963A KR930010987A KR 930010987 A KR930010987 A KR 930010987A KR 1019920020963 A KR1019920020963 A KR 1019920020963A KR 920020963 A KR920020963 A KR 920020963A KR 930010987 A KR930010987 A KR 930010987A
Authority
KR
South Korea
Prior art keywords
circuit
mode
voltage
dynamic ram
address strobe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019920020963A
Other languages
English (en)
Korean (ko)
Inventor
마사노리 다즈노키
시게토시 사코무라
도시쓰구 다케쿠마
유타카 이토우
가즈야 이토우
와타루 아라카와
히데토시 이와이
도시유키 사쿠타
마사미치 이시하라
Original Assignee
가나이 쓰토무
가부시키가이샤 히차치 세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP3327032A external-priority patent/JPH05144258A/ja
Application filed by 가나이 쓰토무, 가부시키가이샤 히차치 세이사쿠쇼 filed Critical 가나이 쓰토무
Publication of KR930010987A publication Critical patent/KR930010987A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
KR1019920020963A 1991-11-15 1992-11-09 다이나믹형 ram의 특수 모드제어방법 Withdrawn KR930010987A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP32703391 1991-11-15
JP91-327033 1991-11-15
JP3327032A JPH05144258A (ja) 1991-11-15 1991-11-15 ダイナミツク型ｒａｍの特殊モード制御方法
JP91-327032 1991-11-15

Publications (1)

Publication Number Publication Date
KR930010987A true KR930010987A (ko) 1993-06-23

Family

ID=26572373

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920020963A Withdrawn KR930010987A (ko) 1991-11-15 1992-11-09 다이나믹형 ram의 특수 모드제어방법

Country Status (4)

Country Link
US (1) US5410507A (https=)
EP (1) EP0542454A3 (https=)
KR (1) KR930010987A (https=)
TW (1) TW212243B (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2725824B1 (fr) * 1994-10-18 1997-01-03 Thomson Csf Semiconducteurs Memoire insensible aux perturbations
JPH08315570A (ja) * 1995-05-15 1996-11-29 Mitsubishi Electric Corp 半導体記憶装置
US5657293A (en) * 1995-08-23 1997-08-12 Micron Technology, Inc. Integrated circuit memory with back end mode disable
US5689467A (en) * 1995-11-30 1997-11-18 Texas Instruments Incorporated Apparatus and method for reducing test time of the data retention parameter in a dynamic random access memory
JPH09167488A (ja) * 1995-12-18 1997-06-24 Mitsubishi Electric Corp 半導体記憶装置
US5640361A (en) * 1996-05-01 1997-06-17 Hewlett-Packard Company Memory architecture
JP3863313B2 (ja) * 1999-03-19 2006-12-27 富士通株式会社 半導体記憶装置
US6563746B2 (en) * 1999-11-09 2003-05-13 Fujitsu Limited Circuit for entering/exiting semiconductor memory device into/from low power consumption mode and method of controlling internal circuit at low power consumption mode
JP2001202773A (ja) * 2000-01-20 2001-07-27 Mitsubishi Electric Corp 半導体記憶装置
JP2002056671A (ja) * 2000-08-14 2002-02-22 Hitachi Ltd ダイナミック型ｒａｍのデータ保持方法と半導体集積回路装置
WO2002032231A1 (en) * 2000-10-19 2002-04-25 Edens, Luppo Protein hydrolysates
US7085186B2 (en) * 2001-04-05 2006-08-01 Purple Mountain Server Llc Method for hiding a refresh in a pseudo-static memory
KR100465597B1 (ko) * 2001-12-07 2005-01-13 주식회사 하이닉스반도체 반도체 메모리 소자의 리프레쉬장치 및 그것의 리프레쉬방법
JP2004133800A (ja) * 2002-10-11 2004-04-30 Renesas Technology Corp 半導体集積回路装置
JP4478974B2 (ja) * 2004-01-30 2010-06-09 エルピーダメモリ株式会社 半導体記憶装置及びそのリフレッシュ制御方法
US7215188B2 (en) * 2005-02-25 2007-05-08 Freescale Semiconductor, Inc. Integrated circuit having a low power mode and method therefor
US8547756B2 (en) 2010-10-04 2013-10-01 Zeno Semiconductor, Inc. Semiconductor memory device having an electrically floating body transistor
KR100870423B1 (ko) * 2007-06-27 2008-11-26 주식회사 하이닉스반도체 반도체메모리소자
US8130547B2 (en) 2007-11-29 2012-03-06 Zeno Semiconductor, Inc. Method of maintaining the state of semiconductor memory having electrically floating body transistor
US10340276B2 (en) 2010-03-02 2019-07-02 Zeno Semiconductor, Inc. Method of maintaining the state of semiconductor memory having electrically floating body transistor
KR102194791B1 (ko) * 2013-08-09 2020-12-28 에스케이하이닉스 주식회사 메모리, 이를 포함하는 메모리 시스템 및 메모리의 동작방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0632217B2 (ja) * 1981-06-29 1994-04-27 富士通株式会社 半導体記憶装置
JPH01205788A (ja) * 1988-02-12 1989-08-18 Toshiba Corp 半導体集積回路
JPH02246516A (ja) * 1989-03-20 1990-10-02 Hitachi Ltd 半導体装置
US5172341A (en) * 1990-01-19 1992-12-15 Dallas Semiconductor Corporation Serial dram controller with multi generation interface

Also Published As

Publication number Publication date
EP0542454A3 (en) 1996-02-14
TW212243B (https=) 1993-09-01
EP0542454A2 (en) 1993-05-19
US5410507A (en) 1995-04-25

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19921109

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid