KR920018640A - Lcd 구동회로 - Google Patents

Lcd 구동회로 Download PDF

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Publication number
KR920018640A
KR920018640A KR1019920001363A KR920001363A KR920018640A KR 920018640 A KR920018640 A KR 920018640A KR 1019920001363 A KR1019920001363 A KR 1019920001363A KR 920001363 A KR920001363 A KR 920001363A KR 920018640 A KR920018640 A KR 920018640A
Authority
KR
South Korea
Prior art keywords
signal
latch
circuit
clock
enable
Prior art date
Application number
KR1019920001363A
Other languages
English (en)
Other versions
KR0162501B1 (ko
Inventor
야스히로 신
데루유끼 후지이
Original Assignee
고스기 노부미쓰
오끼덴끼고오교 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 고스기 노부미쓰, 오끼덴끼고오교 가부시끼가이샤 filed Critical 고스기 노부미쓰
Publication of KR920018640A publication Critical patent/KR920018640A/ko
Application granted granted Critical
Publication of KR0162501B1 publication Critical patent/KR0162501B1/ko

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

내용 없음

Description

LCD 구동회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예를 나타내며 구동회로를 캐스케이드 접속한 상태를 나타낸 회로 구성도,
제2도는 제1도의 각 부의 동작 파형도.

Claims (1)

  1. 데이터 생성회로로부터 시리얼로 주어지는 데이터를 순차적으로 래치하기 위한 플립플롭이 소정수 형성되어 있는 데이터 래치회로와, 상기 데이터 래치회로에 형성되어 있는 각 플립플롭을 래치가능상태로하는 래치신호를 쉬프트 클럭펄스신호에 의하여 순차 보내면서 순번으로 출력하여 최후에 클럭 제어회로에 제1클럭제어신호를 출력하기 위한 소정수의 플립플롭이 형성되어 있는 쉬프트레지스터와, 상기 데이터 생성회로부터 주어지는 래치펄스에 의하여 리셋되어 클럭펄스신호를 분주하는 카운터 회로와, 캐스케이드(cascade) 접속시의 이네이블(enable)신호를 입력하기 위하여 형성된 이네이블 입력단자와, 이네이블 입력단자의 신호를 상기 카운터 회로의 출력신호에 의하여 판독하는 이네이블 래치회로와, 캐스케이드 접속시에 초단으로서 사용할 때 논리레벨 “H”(또는 “L”)을 차단으로 사용할때 논리레벨 “L”(또는 “H”)로 되는 제2클럭제어신호로 하고, 상기 이네이블 래치회로의 출력을 제3제어클럭제어신호로 하며, 상기 제1 ,제2 ,제3클럭제어신호로부터 상기 클럭펄스신호를 제어하여서 상기 쉬프트클럭펄스신호를 출력하는 클럭제어회로와, 상기 래치펄스에 의하여 리셋(또는 세트)되어 상기 카운트회로의 분주수(分周數)에 따라서 선택된 상기 쉬프트레지스터의 래치신호에 의하여 세트(또는 리셋)되는 이네이블 신호출력회로와, 이 이네이블 신호 출력단자와 상기 제2클럭신호에 의하여 래치펄스신호와, 래치펄스신호에 대응하여 발생하는 제2래치펄스신호의 절환을 행하여 상기 래치 이네이블회로, 쉬프트레지스터를 제어하는 래치펄스제어회로를 구비하고, 상기 제2클럭제어신호에 의하여 래치펄스신호 그 자체와 래치펄스신호에 대응하여 발생하는 제2래치펄스를 절환하여서 쉬프트레지스터와 이네이블 래치회로에 출력하여 제어함으로써 외견상 래치펄스의 후연(後緣)에서 작동하여 래치펄스중에 클럭이 입력되어도 동작함을 특징으로 하는 LCD 구동회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019920001363A 1991-03-29 1992-01-30 Lcd 구동회로 KR0162501B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3066777A JP2724053B2 (ja) 1991-03-29 1991-03-29 Ｌｃｄ駆動回路
JP91-066777 1991-03-29

Publications (2)

Publication Number Publication Date
KR920018640A true KR920018640A (ko) 1992-10-22
KR0162501B1 KR0162501B1 (ko) 1999-03-20

Family

ID=13325637

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920001363A KR0162501B1 (ko) 1991-03-29 1992-01-30 Lcd 구동회로

Country Status (5)

Country Link
US (1) US5270696A (ko)
EP (1) EP0506418B1 (ko)
JP (1) JP2724053B2 (ko)
KR (1) KR0162501B1 (ko)
DE (1) DE69216268T2 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461680A (en) * 1993-07-23 1995-10-24 Escom Ag Method and apparatus for converting image data between bit-plane and multi-bit pixel data formats
JP3540844B2 (ja) * 1994-11-02 2004-07-07 日本テキサス・インスツルメンツ株式会社 半導体集積回路
CN100530332C (zh) * 1995-02-01 2009-08-19 精工爱普生株式会社 液晶显示装置
KR0155934B1 (ko) * 1995-12-14 1998-11-16 김광호 엑스.지.에이. 그래픽 시스템
JP3663049B2 (ja) * 1998-05-14 2005-06-22 三洋電機株式会社 表示駆動回路
JP4190706B2 (ja) * 2000-07-03 2008-12-03 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP2002023710A (ja) * 2000-07-06 2002-01-25 Hitachi Ltd 液晶表示装置
KR100435114B1 (ko) * 2001-12-20 2004-06-09 삼성전자주식회사 액정디스플레이장치
JP3930332B2 (ja) * 2002-01-29 2007-06-13 富士通株式会社 集積回路、液晶表示装置、及び信号伝送システム
GB2397710A (en) * 2003-01-25 2004-07-28 Sharp Kk A shift register for an LCD driver, comprising reset-dominant RS flip-flops
US7158420B2 (en) * 2005-04-29 2007-01-02 Macronix International Co., Ltd. Inversion bit line, charge trapping non-volatile memory and method of operating same
CN108447436B (zh) * 2018-03-30 2019-08-09 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、显示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2451237C2 (de) * 1974-10-29 1985-10-10 Texas Instruments Deutschland Gmbh, 8050 Freising Schaltungsanordnung zum Ansteuern einer mehrere Anzeigesegmente enthaltenden, der Anzeige verschiedener Zeichen dienenden Anzeigevorrichtung
JPS5865482A (ja) * 1981-10-15 1983-04-19 株式会社東芝 デ−タ転送制御装置
JPH0634154B2 (ja) * 1983-01-21 1994-05-02 シチズン時計株式会社 マトリクス型表示装置の駆動回路
EP0162969A1 (en) * 1984-05-30 1985-12-04 BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap Switching circuits and matrix device using same
JPS6132093A (ja) * 1984-07-23 1986-02-14 シャープ株式会社 液晶表示装置の駆動回路
JP2511869B2 (ja) * 1986-03-18 1996-07-03 シチズン時計株式会社 液晶表示装置
EP0244978B1 (en) * 1986-04-25 1992-11-04 Seiko Instruments Inc. Interface, for example for a liquid crystal display device
JPH0752327B2 (ja) * 1988-04-22 1995-06-05 三菱電機株式会社 画像表示装置
JPH02163794A (ja) * 1988-12-19 1990-06-25 Mitsubishi Electric Corp 同期信号判別装置
US5021775A (en) * 1989-02-27 1991-06-04 Motorola, Inc. Synchronization method and circuit for display drivers
JPH0339787A (ja) * 1989-07-06 1991-02-20 Sharp Corp 液晶表示装置の駆動回路
JP2642204B2 (ja) * 1989-12-14 1997-08-20 シャープ株式会社 液晶表示装置の駆動回路
EP0432798B1 (en) * 1989-12-15 1995-04-12 Oki Electric Industry Co., Ltd. Driver circuit
JP2997787B2 (ja) * 1989-12-15 2000-01-11 沖電気工業株式会社 駆動回路

Also Published As

Publication number Publication date
EP0506418B1 (en) 1997-01-02
EP0506418A3 (en) 1993-07-14
US5270696A (en) 1993-12-14
EP0506418A2 (en) 1992-09-30
JPH04301679A (ja) 1992-10-26
KR0162501B1 (ko) 1999-03-20
JP2724053B2 (ja) 1998-03-09
DE69216268T2 (de) 1997-07-31
DE69216268D1 (de) 1997-02-13

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