KR920015385A - 쌍방향 입출력단자용 바운더리 스캔셀 - Google Patents

쌍방향 입출력단자용 바운더리 스캔셀 Download PDF

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Publication number
KR920015385A
KR920015385A KR1019920001119A KR920001119A KR920015385A KR 920015385 A KR920015385 A KR 920015385A KR 1019920001119 A KR1019920001119 A KR 1019920001119A KR 920001119 A KR920001119 A KR 920001119A KR 920015385 A KR920015385 A KR 920015385A
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South Korea
Prior art keywords
output
terminals
input
logic circuit
bidirectional
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KR1019920001119A
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English (en)
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KR960000794B1 (ko
Inventor
고지 마츠키
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아오이 죠이치
가부시키가이샤 도시바
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

내용 없음

Description

쌍방향 입출력단자용 바운더리 스캔셀
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 따른 쌍방향 입출력단자용 바운더리 스캔셀의 구성을 도시한 회로도. 제2도는 제1도에 도시한 쌍방향 입출력단자용 바운더리 스캔셀이 갖는 Hi-Z출력형 래치회로의 구성을 도시한 회로도. 제3도는 제1도에 도시한 쌍방향 입출력단자용 바운더리 스캔셀을 논리블럭에 접속한 구성을 도시한 블럭도.

Claims (1)

  1. 시험할 논리회로의 쌍방향 입출력단자에 접속되는 2개의 단자(D1,D2)와 ; 이 단자(D1,D2) 사이에 접속되면서, 상기 논리회로가 통상 동작을 행하는 경우에는 온되어 상기 단자(D1,D2)를 전기적으로 상호 접속시키는 한편, 상기 논리회로가 시험되는 경우에는 오프되어 상기 단자(D1,D2)를 전기적으로 분리하는 아날로그스위치(TG12) ; 상기 논리회로가 통상 동작을 행할 때에는 출력이 하이임피던스로 되는 한편 상기 논리회로가 시험될 때에는 상기 쌍방향 입출력단자의 입출력모드에 따라 출력이 하이임피던스 또는 로우임피던스로 되어, 상기 논리회로에 공급할 테스트데이터를 격납하는 제 1 래치회로(L2,L4) ; 테스트데이터를 받아들임과 더불어 상기 논리회로로부터의 테스트결과를 격납하는 제 2 래치회로(L1,L3) ;상기 쌍방향 입출력단자가 입력모드일 때에는 상기 제 1 래치회로(L2,L4)의 출력을 로우임피던스로 만들고, 상기 쌍방향입출력단자가 출력모드일 때에는 상기 제 1 래치회로(L2,L4)의 출력을 하이임피던스로 만드는 입출력모드의 설정데이터를격납하는 제 3 래치회로(L6,L8) 및 ; 상기 입출력모드의 설정데이터를 받아들이는 제 4 래치회로(L5,L7)를 구비하여 구성된 것을 특징으로 하는 쌍방향 입출력단자용 바운더리 스캔셀.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019920001119A 1991-01-28 1992-01-27 쌍방향 입출력단자용 바운더리 스캔셀 KR960000794B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3008652A JP2535670B2 (ja) 1991-01-28 1991-01-28 双方向入出力端子用バウンダリスキャンセル
JP91-008652 1991-01-28

Publications (2)

Publication Number Publication Date
KR920015385A true KR920015385A (ko) 1992-08-26
KR960000794B1 KR960000794B1 (ko) 1996-01-12

Family

ID=11698868

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920001119A KR960000794B1 (ko) 1991-01-28 1992-01-27 쌍방향 입출력단자용 바운더리 스캔셀

Country Status (3)

Country Link
US (1) US5220281A (ko)
JP (1) JP2535670B2 (ko)
KR (1) KR960000794B1 (ko)

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EP0597926A1 (de) * 1991-08-08 1994-05-25 Siemens Aktiengesellschaft Verfahren zur prüfung von integrierten schaltkreisen mit mindestens einer logikschaltung und prüfbarer integrierter schaltkreis
US5528610A (en) * 1992-04-30 1996-06-18 Hughes Aircraft Company Boundary test cell with self masking capability
US5450415A (en) * 1992-11-25 1995-09-12 Matsushita Electric Industrial Co., Ltd. Boundary scan cell circuit and boundary scan test circuit
JP2639319B2 (ja) * 1993-09-22 1997-08-13 日本電気株式会社 半導体装置
JP2727930B2 (ja) * 1993-10-04 1998-03-18 日本電気株式会社 バウンダリスキャンテスト回路
US5617531A (en) * 1993-11-02 1997-04-01 Motorola, Inc. Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
US5513186A (en) * 1993-12-07 1996-04-30 Sun Microsystems, Inc. Method and apparatus for interconnect testing without speed degradation
FR2720205B1 (fr) * 1994-05-20 1996-07-12 Sgs Thomson Microelectronics Cellule pour registre à décalage.
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation
US6694465B1 (en) * 1994-12-16 2004-02-17 Texas Instruments Incorporated Low overhead input and output boundary scan cells
CA2245549C (en) * 1996-02-06 2003-04-08 Telefonaktiebolaget Lm Ericsson Assembly and method for testing integrated circuit devices
US5958076A (en) * 1996-10-29 1999-09-28 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
US5774476A (en) * 1997-02-03 1998-06-30 Motorola, Inc. Timing apparatus and timing method for wrapper cell speed path testing of embedded cores within an integrated circuit
US5889788A (en) * 1997-02-03 1999-03-30 Motorola, Inc. Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation
US5978944A (en) * 1997-11-26 1999-11-02 Intel Corporation Method and apparatus for scan testing dynamic circuits
JP2001084787A (ja) * 1999-09-09 2001-03-30 Oki Electric Ind Co Ltd 不揮発性記憶装置の書き換え回路，不揮発性記憶装置の書き換え方法およびスキャンレジスタ
WO2003093843A1 (en) * 2002-05-01 2003-11-13 Logicvision(Canada), Inc Circuit and method for adding parametric test capability to digital boundary scan
US20040199838A1 (en) * 2003-03-19 2004-10-07 Rutkowski Paul William Enhanced boundary-scan method and apparatus providing tester channel reduction
US8615694B2 (en) * 2011-02-07 2013-12-24 Texas Instruments Incorporated Interposer TAP boundary register coupling stacked die functional input/output data

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US4554664A (en) * 1983-10-06 1985-11-19 Sperry Corporation Static memory cell with dynamic scan test latch
KR910002236B1 (ko) * 1986-08-04 1991-04-08 미쓰비시 뎅기 가부시끼가이샤 반도체집적회로장치
US4833676A (en) * 1987-07-30 1989-05-23 Hughes Aircraft Company Interleaved method and circuitry for testing for stuck open faults
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JPH073461B2 (ja) * 1989-03-08 1995-01-18 株式会社東芝 デジタル論理ブロックのテスト回路
US5042034A (en) * 1989-10-27 1991-08-20 International Business Machines Corporation By-pass boundary scan design

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Publication number Publication date
JP2535670B2 (ja) 1996-09-18
US5220281A (en) 1993-06-15
JPH04250370A (ja) 1992-09-07
KR960000794B1 (ko) 1996-01-12

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