KR900002177A - 기호압축회로 - Google Patents
기호압축회로 Download PDFInfo
- Publication number
- KR900002177A KR900002177A KR1019890009922A KR890009922A KR900002177A KR 900002177 A KR900002177 A KR 900002177A KR 1019890009922 A KR1019890009922 A KR 1019890009922A KR 890009922 A KR890009922 A KR 890009922A KR 900002177 A KR900002177 A KR 900002177A
- Authority
- KR
- South Korea
- Prior art keywords
- test
- circuit
- compression circuit
- perform
- output register
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/40—Response verification devices using compression techniques
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 제 1 실시예에 따른 구성을 나타낸 도면.
제 2 도는 본 발명의 제 2 실시예에 따른 구성을 나타낸 도면.
제 3 도는 출력레지스터를 이용한 조합회로의 테스트에 대한 개략구성을 나타낸 도면.
Claims (1)
- 해석대상으로 되는 피테스트회로(21)로부터 복수의 테스트출력을 취입하는 출력레지스터(31)가 병렬기호압축동작을 수행할 수 있도록 된 기호압축회로에 있어서, 상기 출력레지스터(31)가 스캔동작을 수행하도록 공통의 제어신호(A, B)를 인가받아 상기 피테스트회로(21)의 테스트출력을 소정의 논리레벨로 설정하는 트랜지스터(37)를 갖추어 구성된 것을 특징으로 하는 기호압축회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP88-171906 | 1988-07-12 | ||
JP63-171906 | 1988-07-12 | ||
JP63171906A JPH0776782B2 (ja) | 1988-07-12 | 1988-07-12 | シグネチャ圧縮回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900002177A true KR900002177A (ko) | 1990-02-28 |
KR920004278B1 KR920004278B1 (ko) | 1992-06-01 |
Family
ID=15932020
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890009922A KR920004278B1 (ko) | 1988-07-12 | 1989-07-12 | 기호압축회로 |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0350888B1 (ko) |
JP (1) | JPH0776782B2 (ko) |
KR (1) | KR920004278B1 (ko) |
DE (1) | DE68927207T2 (ko) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4975640A (en) * | 1990-02-20 | 1990-12-04 | Crosscheck Technology, Inc. | Method for operating a linear feedback shift register as a serial shift register with a crosscheck grid structure |
JPH0469580A (ja) * | 1990-07-10 | 1992-03-04 | Nec Corp | 並列パタン圧縮器 |
GB9911043D0 (en) * | 1999-05-12 | 1999-07-14 | Sgs Thomson Microelectronics | Memory circuit |
JP2002100738A (ja) | 2000-09-25 | 2002-04-05 | Toshiba Corp | 半導体集積回路及びテスト容易化回路の自動挿入方法 |
CA2348799A1 (fr) * | 2001-05-22 | 2002-11-22 | Marcel Blais | Appareil d'essai de composants electroniques |
KR100825790B1 (ko) * | 2006-11-07 | 2008-04-29 | 삼성전자주식회사 | 데이터를 압축시키는 테스트 콘트롤러를 채용한 테스트시스템, 데이터 압축 회로 및 테스트 방법 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4377757A (en) * | 1980-02-11 | 1983-03-22 | Siemens Aktiengesellschaft | Logic module for integrated digital circuits |
DE3215671C2 (de) * | 1982-04-27 | 1984-05-03 | Siemens AG, 1000 Berlin und 8000 München | Programmierbare Logikanordnung |
JPS59200456A (ja) * | 1983-04-27 | 1984-11-13 | Hitachi Ltd | 半導体集積回路装置 |
US4680539A (en) * | 1983-12-30 | 1987-07-14 | International Business Machines Corp. | General linear shift register |
GB8432533D0 (en) * | 1984-12-21 | 1985-02-06 | Plessey Co Plc | Integrated circuits |
US4768196A (en) * | 1986-10-28 | 1988-08-30 | Silc Technologies, Inc. | Programmable logic array |
-
1988
- 1988-07-12 JP JP63171906A patent/JPH0776782B2/ja not_active Expired - Fee Related
-
1989
- 1989-07-12 EP EP89112727A patent/EP0350888B1/en not_active Expired - Lifetime
- 1989-07-12 DE DE68927207T patent/DE68927207T2/de not_active Expired - Fee Related
- 1989-07-12 KR KR1019890009922A patent/KR920004278B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0350888A2 (en) | 1990-01-17 |
JPH0222579A (ja) | 1990-01-25 |
KR920004278B1 (ko) | 1992-06-01 |
EP0350888A3 (en) | 1991-08-21 |
DE68927207D1 (de) | 1996-10-24 |
JPH0776782B2 (ja) | 1995-08-16 |
DE68927207T2 (de) | 1997-03-06 |
EP0350888B1 (en) | 1996-09-18 |
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A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030530 Year of fee payment: 12 |
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LAPS | Lapse due to unpaid annual fee |