KR910018916A - 정보처리장치 - Google Patents
정보처리장치 Download PDFInfo
- Publication number
- KR910018916A KR910018916A KR1019910006530A KR910006530A KR910018916A KR 910018916 A KR910018916 A KR 910018916A KR 1019910006530 A KR1019910006530 A KR 1019910006530A KR 910006530 A KR910006530 A KR 910006530A KR 910018916 A KR910018916 A KR 910018916A
- Authority
- KR
- South Korea
- Prior art keywords
- output
- selection control
- information processing
- control means
- state
- Prior art date
Links
- 230000010365 information processing Effects 0.000 title claims description 4
- 230000005540 biological transmission Effects 0.000 claims 3
- 238000012360 testing method Methods 0.000 claims 3
- 238000007689 inspection Methods 0.000 claims 2
- 230000001404 mediated effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 따른 정보처리장치의 요부구성을 나타낸 도면, 제2도는 제1도에 도시된 장치의 타이밍 차트.
Claims (2)
- 복수의 기능요소(1a, 1b)가 각각 대응되는 출력수단(3a, 3b)을 매개하여 공통의 전송로(4)에 접속되며, 명령을 실행처리하는 상태 및 기능을 검사·시험하는 상태를 가지는 정보처리장치에 있어서, 명령을 실행처리하는 상태에 있어 상기 출력수단(3a, 3b)을 택일적으로 선택하고, 선택된 상기 출력수단에 대응된 상기 기능요소의 출력을 선택된 상기 출력수단을 매개하여 상기 전송로(4)에 부여하는 제1선택제어수단(2)과, 검사·시험상태에 있어서, 상기 출력수단(3a, 3b)을 택일적으로 선택하고, 선택된 상기 출력수단에 대응된 상기 기능요소의 출력을 선택된 상기 출력수단을 매개하여 상기 전송로(4)에 부여하는 제2선택제어수단(6a, 6b)을 구비하여 구성된 것을 특징으로 하는 정보처리장치.
- 제1항에 있어서, 상기 제2선택제어수단(6a, 6b)은 검사·시험상태에 있어 상기 제1선택제어수단(2)의 출력을 거두어 들여서 보존·유지시키고, 보존·유지한 상기 출력을 독출하는 것을 특징으로 하는 정보처리장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP02-106429 | 1990-04-24 | ||
JP2106429A JPH0719217B2 (ja) | 1990-04-24 | 1990-04-24 | 情報処理装置 |
JP2-106429 | 1990-04-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910018916A true KR910018916A (ko) | 1991-11-30 |
KR940004332B1 KR940004332B1 (ko) | 1994-05-19 |
Family
ID=14433417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910006530A KR940004332B1 (ko) | 1990-04-24 | 1991-04-24 | 정보처리장치 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5515517A (ko) |
EP (1) | EP0454052B1 (ko) |
JP (1) | JPH0719217B2 (ko) |
KR (1) | KR940004332B1 (ko) |
DE (1) | DE69130079T2 (ko) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4964118A (en) * | 1988-10-24 | 1990-10-16 | Northern Telecom Limited | Apparatus and method for echo cancellation |
JP2643789B2 (ja) * | 1993-09-01 | 1997-08-20 | 日本電気株式会社 | スキャンパス回路 |
US6016564A (en) * | 1996-08-28 | 2000-01-18 | Matsushita Electric Industrial Co., Ltd. | Method of design for testability, method of design for avoiding bus error and integrated circuit |
JP2000346905A (ja) * | 1999-06-04 | 2000-12-15 | Nec Corp | 半導体装置およびそのテスト方法 |
US6560663B1 (en) * | 1999-09-02 | 2003-05-06 | Koninklijke Philips Electronics N.V. | Method and system for controlling internal busses to prevent bus contention during internal scan testing |
US6523075B1 (en) * | 1999-09-02 | 2003-02-18 | Koninklijke Philips Electronics N.V. | Method and system for controlling internal busses to prevent busses contention during internal scan testing by using a centralized control resource |
US6487688B1 (en) | 1999-12-23 | 2002-11-26 | Logicvision, Inc. | Method for testing circuits with tri-state drivers and circuit for use therewith |
JP5014899B2 (ja) * | 2007-07-02 | 2012-08-29 | ルネサスエレクトロニクス株式会社 | 再構成可能デバイス |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CH632365A5 (de) * | 1978-01-30 | 1982-09-30 | Patelhold Patentverwertung | Datenaustauschverfahren zwischen mehreren partnern. |
JPS57114924A (en) * | 1981-01-09 | 1982-07-17 | Toshiba Corp | Bus control system |
FR2503899A1 (fr) * | 1981-04-08 | 1982-10-15 | Thomson Csf | Procede et dispositif de transmission de donnees numeriques |
US4535330A (en) * | 1982-04-29 | 1985-08-13 | Honeywell Information Systems Inc. | Bus arbitration logic |
US5247521A (en) * | 1986-04-23 | 1993-09-21 | Hitachi, Ltd. | Data processor |
JPH06105285B2 (ja) * | 1986-08-22 | 1994-12-21 | 三菱電機株式会社 | 半導体集積回路装置 |
JP2628154B2 (ja) * | 1986-12-17 | 1997-07-09 | 富士通株式会社 | 半導体集積回路 |
JPH0821011B2 (ja) * | 1987-06-03 | 1996-03-04 | 株式会社日立製作所 | バス拡張制御方式 |
US5101498A (en) * | 1987-12-31 | 1992-03-31 | Texas Instruments Incorporated | Pin selectable multi-mode processor |
JP2633900B2 (ja) * | 1988-04-22 | 1997-07-23 | 株式会社日立製作所 | 共通バス制御方法 |
JP2501874B2 (ja) * | 1988-06-30 | 1996-05-29 | 三菱電機株式会社 | Icカ―ド |
US4987529A (en) * | 1988-08-11 | 1991-01-22 | Ast Research, Inc. | Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters |
US4973904A (en) * | 1988-12-12 | 1990-11-27 | Ncr Corporation | Test circuit and method |
US4980889A (en) * | 1988-12-29 | 1990-12-25 | Deguise Wayne J | Multi-mode testing systems |
US5210864A (en) * | 1989-06-01 | 1993-05-11 | Mitsubishi Denki Kabushiki Kaisha | Pipelined microprocessor with instruction execution control unit which receives instructions from separate path in test mode for testing instruction execution pipeline |
US5115435A (en) * | 1989-10-19 | 1992-05-19 | Ncr Corporation | Method and apparatus for bus executed boundary scanning |
JPH07113655B2 (ja) * | 1989-11-28 | 1995-12-06 | 株式会社東芝 | テスト容易化回路 |
US5157781A (en) * | 1990-01-02 | 1992-10-20 | Motorola, Inc. | Data processor test architecture |
US5331571A (en) * | 1992-07-22 | 1994-07-19 | Nec Electronics, Inc. | Testing and emulation of integrated circuits |
-
1990
- 1990-04-24 JP JP2106429A patent/JPH0719217B2/ja not_active Expired - Fee Related
-
1991
- 1991-04-23 DE DE69130079T patent/DE69130079T2/de not_active Expired - Lifetime
- 1991-04-23 EP EP91106509A patent/EP0454052B1/en not_active Expired - Lifetime
- 1991-04-24 KR KR1019910006530A patent/KR940004332B1/ko not_active IP Right Cessation
-
1994
- 1994-12-14 US US08/357,052 patent/US5515517A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH045734A (ja) | 1992-01-09 |
JPH0719217B2 (ja) | 1995-03-06 |
EP0454052A2 (en) | 1991-10-30 |
DE69130079T2 (de) | 1999-02-18 |
KR940004332B1 (ko) | 1994-05-19 |
DE69130079D1 (de) | 1998-10-08 |
US5515517A (en) | 1996-05-07 |
EP0454052A3 (en) | 1992-12-09 |
EP0454052B1 (en) | 1998-09-02 |
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E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030430 Year of fee payment: 10 |
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LAPS | Lapse due to unpaid annual fee |