KR920007133A - 표면 장착중에 균열을 방지하기 위한 집적 회로 디바이스 및 그 방법 - Google Patents

표면 장착중에 균열을 방지하기 위한 집적 회로 디바이스 및 그 방법 Download PDF

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Publication number
KR920007133A
KR920007133A KR1019910016546A KR910016546A KR920007133A KR 920007133 A KR920007133 A KR 920007133A KR 1019910016546 A KR1019910016546 A KR 1019910016546A KR 910016546 A KR910016546 A KR 910016546A KR 920007133 A KR920007133 A KR 920007133A
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South Korea
Prior art keywords
chip
semiconductor
lead
lead frame
integrated circuit
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KR1019910016546A
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English (en)
Inventor
지. 하이넨 캐서린
Original Assignee
엔. 라이스 머레트
텍사스 인스트루먼트츠 인코포레이티드
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Application filed by 엔. 라이스 머레트, 텍사스 인스트루먼트츠 인코포레이티드 filed Critical 엔. 라이스 머레트
Publication of KR920007133A publication Critical patent/KR920007133A/ko

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract

내용 없음

Description

표면 장착중에 균열을 방지하기 위한 집적 회로 디바이스 및 그 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 전형적인 집적회로 디바이스 패키지를 도시한 단면도,
제2도는 리드 프레임, 접착 테이프 및 반도체 칩을 나타낸 리드오버 칩 중앙 본드 디바이스의 분해 사시도,
제2a도는 반도체 칩의 접속 상태를 나타낸 리드 오버 칩 중앙본드 디바이스의 정면도.
제2b도는 와이어 본드 접속을 나타낸 리드 오버 칩 중앙본드 디바이스의 정면도.
제2c도는 봉입 몰드 화합물이 투명한 리드 오버 칩 중앙본드 디바이스의 정면도.
제2d도는 완성될 리드 오버 칩 중앙본드 패키지의 측면도.
제2e도는 완성된 리드 오버 칩 중앙본드 집적 회로 패키지를 부분적으로 절취하여 도시한 사시도.
제3도는 봉입물질의 균일 상태를 나타낸 LOC 패키지의 단면도.
제4도는 반도체 칩의 비활성 면상의 아미노프로필트리에톡시실란 코팅을 나타낸 LOC 패키지의 단면도.

Claims (9)

  1. 리드 오버 칩 리드 프레임을 장착시키기에 적합한 반도체 집적 회로 칩에 있어서, 리드 오버 칩 리드 프레임에 부착된 활성 면과 비활성 배면을 포함하는 집적 회로 칩 및 집적 회로 칩의 비활성 배면상의 아미노프로필트리에톡시실란 코팅막을 포함하는 것을 특징으로 하는 반도체 집적 회로 칩.
  2. 제1항에 있어서, 상기 아미노프로필트리에톡시실란 코팅막의 두께가 1미크론 이하인 것을 특징으로 하는 반도체 집적 회로 칩.
  3. 활성면 및 배면을 갖고 있는 반도체 회로 칩, 상기 반도체 칩을 지지하고 외부 접속부를 제공하며, 한 단부에 의해 반도체 칩에 접속된 리드 핑거를 포함하는 리드 프레임 및 반도체 칩, 리드 프레임, 봉입물을 거쳐 연장하는 리드 핑거의 다른 단부들을 봉입시키는 봉입물을 포함하고, 상기 반도체 칩이 봉입물에 대한 접착력을 촉진시키기 위해 배면상에 아미노프로필트리에톡시실란층을 포함하는 것을 특징으로 하는 반도체 패키지 디바이스.
  4. 제3항에 있어서, 상기 아미노프로필트리에톡시실란층의 두께가 1미크론 까지인 것을 특징으로 하는 반도체 패키지 디바이스.
  5. 제4항에 있어서, 상기 봉입물이 플라스틱인 것을 특징으로 하는 반도체 패키지 디바이스.
  6. 제5항에 있어서, 사기 리드 프레임이 리드 오버 칩 리드 프레임인 것을 특징으로 하는 반도체 패키지 디바이스.
  7. 제5항에 있어서, 상기 리드 프레임이 탭팩 테이프인 것을 특징으로 하는 반도체 패키지 디바이스.
  8. 제5항에 있어서, 상기 리드 프레임이 플립 칩 리드 프레임인 것을 특징으로 하는 반도체 패키지 디바이스.
  9. 인쇄 회로 기판의 표면 장착중에 패키지 균열에 저항력이 있는 반도체 패키지 디바이스를 제조하는 방법에 있어서, 반도체 칩의 활성 측면을 리드 오버 칩 리드 프레임에 접속시키는 단계, 아미노프로필트리에톡시실란막을 반도체 칩의 비활성 측면에 제공하는 단계 및 인쇄 회로 기판에 표면 장착되는 패키지 디바이스를 형성하기 위한 형태로 플라스틱으로 반도체 및 리드 오버 칩 리드 프레임을 패키징시키는 단계를 포함하는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019910016546A 1990-09-24 1991-09-20 표면 장착중에 균열을 방지하기 위한 집적 회로 디바이스 및 그 방법 KR920007133A (ko)

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US07/586,821 US5227661A (en) 1990-09-24 1990-09-24 Integrated circuit device having an aminopropyltriethoxysilane coating
US586,821 1990-09-24

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