KR910013262A - 반도체 메모리 어레이의 워드라인 배열방법 - Google Patents

반도체 메모리 어레이의 워드라인 배열방법 Download PDF

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Publication number
KR910013262A
KR910013262A KR1019890020102A KR890020102A KR910013262A KR 910013262 A KR910013262 A KR 910013262A KR 1019890020102 A KR1019890020102 A KR 1019890020102A KR 890020102 A KR890020102 A KR 890020102A KR 910013262 A KR910013262 A KR 910013262A
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KR
South Korea
Prior art keywords
semiconductor memory
lines
adjacent
memory device
twisted
Prior art date
Application number
KR1019890020102A
Other languages
English (en)
Other versions
KR930001737B1 (ko
Inventor
민동선
조수인
진대제
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890020102A priority Critical patent/KR930001737B1/ko
Priority to NL9000431A priority patent/NL194178C/nl
Priority to DE4005992A priority patent/DE4005992C2/de
Priority to FR9002485A priority patent/FR2656726B1/fr
Priority to GB9004448A priority patent/GB2239556B/en
Priority to US07/488,740 priority patent/US5155700A/en
Priority to JP2096599A priority patent/JPH0783060B2/ja
Priority to CN90106626A priority patent/CN1021997C/zh
Priority to IT48189A priority patent/IT1241524B/it
Publication of KR910013262A publication Critical patent/KR910013262A/ko
Application granted granted Critical
Publication of KR930001737B1 publication Critical patent/KR930001737B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.

Description

반도체 메모리 어레이의 워드라인 배열방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 워드라인 구성도,
제3(B)도는 제2도에 따른 워드라인의 용량성분 표시도.

Claims (5)

  1. 다수의 워드라인들을 구비하는 반도체 메모리 어레이에 있어서, 상기워드라인들이 최소한 4개이상으로 하나의 조를 형성하여 각 조에 있는 워드라인들이 최초에 인접한 워드라인과는 서로 인접하지 않도록 꼬여 있음을 특징으로 하는 반도체 메모리 장치.
  2. 제1항에 있어서, 상기 워드라인들이 한번 꼬인 후에도 최초에 인접한 워드라인끼리는 서로 인접하지 않도록 2회 이상 꼬여질 수 있음을 특징으로 하는 반도체 메모리 장치.
  3. 제1항에 있어서, 상기 워드라인들이 워드라인 스트래핑영역에서 꼬이게 됨을 특징으로 하는 반도체 메모리 장치.
  4. 다수개의 선로들로 구성된 여러종류의 신호선로들을 구비하는 반도체 메모리 장치에 있어서, 상기 선로들을 4개 이상의 다수개로써 하나의 조를 만들고, 상기 각 조에 있는 선로들이 동일한 조에 있는 최초에 인접한 선로들과는 인접하지 않도록 꼬아줌을 특징으로 하는 반도체 메모리.
  5. 제4항에 있어서, 상기 선로들이 한번 꼬인 후에도 최초에 인접한 선로끼리 서로 인접하지 않도록 2회 이상 꼬여질 수 있음을 특징으로 하는 반도체 메모리 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890020102A 1989-12-29 1989-12-29 반도체 메모리 어레이의 워드라인 배열방법 KR930001737B1 (ko)

Priority Applications (9)

Application Number Priority Date Filing Date Title
KR1019890020102A KR930001737B1 (ko) 1989-12-29 1989-12-29 반도체 메모리 어레이의 워드라인 배열방법
NL9000431A NL194178C (nl) 1989-12-29 1990-02-22 Halfgeleidergeheugeneenheid.
DE4005992A DE4005992C2 (de) 1989-12-29 1990-02-26 Halbleiterspeichervorrichtung mit verringertem Wortleitungskopplungsrauschen
GB9004448A GB2239556B (en) 1989-12-29 1990-02-28 Semiconductor memory device
FR9002485A FR2656726B1 (fr) 1989-12-29 1990-02-28 Structure de lignes de mots interdigitees et croisees destinee a des memoires a semiconducteurs.
US07/488,740 US5155700A (en) 1989-12-29 1990-02-28 Method for reducing coupling noise of word lines in a semiconductor memory device
JP2096599A JPH0783060B2 (ja) 1989-12-29 1990-04-13 半導体メモリ装置のワードライン配列方法
CN90106626A CN1021997C (zh) 1989-12-29 1990-07-31 半导体存储设备
IT48189A IT1241524B (it) 1989-12-29 1990-07-31 Metodo per ridurre il rumore di accoppiamento su linee di parola in undispositivo di memoria a semiconduttori

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020102A KR930001737B1 (ko) 1989-12-29 1989-12-29 반도체 메모리 어레이의 워드라인 배열방법

Publications (2)

Publication Number Publication Date
KR910013262A true KR910013262A (ko) 1991-08-08
KR930001737B1 KR930001737B1 (ko) 1993-03-12

Family

ID=19294143

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890020102A KR930001737B1 (ko) 1989-12-29 1989-12-29 반도체 메모리 어레이의 워드라인 배열방법

Country Status (9)

Country Link
US (1) US5155700A (ko)
JP (1) JPH0783060B2 (ko)
KR (1) KR930001737B1 (ko)
CN (1) CN1021997C (ko)
DE (1) DE4005992C2 (ko)
FR (1) FR2656726B1 (ko)
GB (1) GB2239556B (ko)
IT (1) IT1241524B (ko)
NL (1) NL194178C (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0713864B2 (ja) * 1989-09-27 1995-02-15 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
JPH03171662A (ja) * 1989-11-29 1991-07-25 Sharp Corp 信号線システム
JPH04271086A (ja) * 1991-02-27 1992-09-28 Nec Corp 半導体集積回路
US5297094A (en) * 1991-07-17 1994-03-22 Sgs-Thomson Microelectronics, Inc. Integrated circuit memory device with redundant rows
US5311477A (en) * 1991-07-17 1994-05-10 Sgs-Thomson Microelectronics, Inc. Integrated circuit memory device having flash clear
US5287322A (en) * 1991-07-17 1994-02-15 Sgs-Thomson Microelectronics, Inc. Integrated circuit dual-port memory device having reduced capacitance
JP2000340766A (ja) * 1999-05-31 2000-12-08 Fujitsu Ltd 半導体記憶装置
US6327170B1 (en) * 1999-09-28 2001-12-04 Infineon Technologies Ag Reducing impact of coupling noise in multi-level bitline architecture
US6567329B2 (en) * 2001-08-28 2003-05-20 Intel Corporation Multiple word-line accessing and accessor
US6563727B1 (en) * 2002-07-31 2003-05-13 Alan Roth Method and structure for reducing noise effects in content addressable memories
US7244995B2 (en) * 2004-10-18 2007-07-17 Texas Instruments Incorporated Scrambling method to reduce wordline coupling noise
US7952901B2 (en) * 2007-08-09 2011-05-31 Qualcomm Incorporated Content addressable memory
US20090154215A1 (en) * 2007-12-14 2009-06-18 Spansion Llc Reducing noise and disturbance between memory storage elements using angled wordlines
JP5612803B2 (ja) * 2007-12-25 2014-10-22 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置
US8411479B2 (en) * 2009-07-23 2013-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuits, systems, and methods for routing the memory circuits
CN113270130A (zh) * 2020-05-29 2021-08-17 台湾积体电路制造股份有限公司 存储器设备

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57208691A (en) * 1981-06-15 1982-12-21 Mitsubishi Electric Corp Semiconductor memory
JPS59124092A (ja) * 1982-12-29 1984-07-18 Fujitsu Ltd メモリ装置
US4729119A (en) * 1984-05-21 1988-03-01 General Computer Corporation Apparatus and methods for processing data through a random access memory system
US4733374A (en) * 1985-03-30 1988-03-22 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device
CA1305255C (en) * 1986-08-25 1992-07-14 Joseph Lebowitz Marching interconnecting lines in semiconductor integrated circuits
JPS63153792A (ja) * 1986-12-17 1988-06-27 Sharp Corp 半導体メモリ装置
JPH0713858B2 (ja) * 1988-08-30 1995-02-15 三菱電機株式会社 半導体記憶装置

Also Published As

Publication number Publication date
IT1241524B (it) 1994-01-17
GB2239556B (en) 1993-08-25
CN1021997C (zh) 1993-09-01
IT9048189A0 (it) 1990-07-31
JPH0783060B2 (ja) 1995-09-06
US5155700A (en) 1992-10-13
GB2239556A (en) 1991-07-03
NL194178B (nl) 2001-04-02
FR2656726B1 (fr) 1995-02-03
DE4005992C2 (de) 1994-01-27
NL9000431A (nl) 1991-07-16
CN1052967A (zh) 1991-07-10
DE4005992A1 (de) 1991-07-11
IT9048189A1 (it) 1992-01-31
NL194178C (nl) 2001-08-03
GB9004448D0 (en) 1990-04-25
FR2656726A1 (fr) 1991-07-05
KR930001737B1 (ko) 1993-03-12
JPH03203369A (ja) 1991-09-05

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