IT1241524B - Metodo per ridurre il rumore di accoppiamento su linee di parola in undispositivo di memoria a semiconduttori - Google Patents
Metodo per ridurre il rumore di accoppiamento su linee di parola in undispositivo di memoria a semiconduttoriInfo
- Publication number
- IT1241524B IT1241524B IT48189A IT4818990A IT1241524B IT 1241524 B IT1241524 B IT 1241524B IT 48189 A IT48189 A IT 48189A IT 4818990 A IT4818990 A IT 4818990A IT 1241524 B IT1241524 B IT 1241524B
- Authority
- IT
- Italy
- Prior art keywords
- memory device
- semiconductor memory
- word lines
- couple noise
- reduce couple
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890020102A KR930001737B1 (ko) | 1989-12-29 | 1989-12-29 | 반도체 메모리 어레이의 워드라인 배열방법 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| IT9048189A0 IT9048189A0 (it) | 1990-07-31 |
| IT9048189A1 IT9048189A1 (it) | 1992-01-31 |
| IT1241524B true IT1241524B (it) | 1994-01-17 |
Family
ID=19294143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT48189A IT1241524B (it) | 1989-12-29 | 1990-07-31 | Metodo per ridurre il rumore di accoppiamento su linee di parola in undispositivo di memoria a semiconduttori |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US5155700A (it) |
| JP (1) | JPH0783060B2 (it) |
| KR (1) | KR930001737B1 (it) |
| CN (1) | CN1021997C (it) |
| DE (1) | DE4005992C2 (it) |
| FR (1) | FR2656726B1 (it) |
| GB (1) | GB2239556B (it) |
| IT (1) | IT1241524B (it) |
| NL (1) | NL194178C (it) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0713864B2 (ja) * | 1989-09-27 | 1995-02-15 | 東芝マイクロエレクトロニクス株式会社 | 半導体記憶装置 |
| JPH03171662A (ja) * | 1989-11-29 | 1991-07-25 | Sharp Corp | 信号線システム |
| JPH04271086A (ja) * | 1991-02-27 | 1992-09-28 | Nec Corp | 半導体集積回路 |
| US5311477A (en) * | 1991-07-17 | 1994-05-10 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit memory device having flash clear |
| US5297094A (en) * | 1991-07-17 | 1994-03-22 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit memory device with redundant rows |
| US5287322A (en) * | 1991-07-17 | 1994-02-15 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit dual-port memory device having reduced capacitance |
| JP2000340766A (ja) * | 1999-05-31 | 2000-12-08 | Fujitsu Ltd | 半導体記憶装置 |
| US6327170B1 (en) * | 1999-09-28 | 2001-12-04 | Infineon Technologies Ag | Reducing impact of coupling noise in multi-level bitline architecture |
| US6567329B2 (en) * | 2001-08-28 | 2003-05-20 | Intel Corporation | Multiple word-line accessing and accessor |
| US6563727B1 (en) * | 2002-07-31 | 2003-05-13 | Alan Roth | Method and structure for reducing noise effects in content addressable memories |
| US7244995B2 (en) * | 2004-10-18 | 2007-07-17 | Texas Instruments Incorporated | Scrambling method to reduce wordline coupling noise |
| US7952901B2 (en) * | 2007-08-09 | 2011-05-31 | Qualcomm Incorporated | Content addressable memory |
| US20090154215A1 (en) * | 2007-12-14 | 2009-06-18 | Spansion Llc | Reducing noise and disturbance between memory storage elements using angled wordlines |
| JP5612803B2 (ja) * | 2007-12-25 | 2014-10-22 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | 半導体記憶装置 |
| US8411479B2 (en) * | 2009-07-23 | 2013-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuits, systems, and methods for routing the memory circuits |
| CN113270130A (zh) * | 2020-05-29 | 2021-08-17 | 台湾积体电路制造股份有限公司 | 存储器设备 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57208691A (en) * | 1981-06-15 | 1982-12-21 | Mitsubishi Electric Corp | Semiconductor memory |
| JPS59124092A (ja) * | 1982-12-29 | 1984-07-18 | Fujitsu Ltd | メモリ装置 |
| US4729119A (en) * | 1984-05-21 | 1988-03-01 | General Computer Corporation | Apparatus and methods for processing data through a random access memory system |
| US4733374A (en) * | 1985-03-30 | 1988-03-22 | Kabushiki Kaisha Toshiba | Dynamic semiconductor memory device |
| CA1305255C (en) * | 1986-08-25 | 1992-07-14 | Joseph Lebowitz | Marching interconnecting lines in semiconductor integrated circuits |
| JPS63153792A (ja) * | 1986-12-17 | 1988-06-27 | Sharp Corp | 半導体メモリ装置 |
| JPH0713858B2 (ja) * | 1988-08-30 | 1995-02-15 | 三菱電機株式会社 | 半導体記憶装置 |
-
1989
- 1989-12-29 KR KR1019890020102A patent/KR930001737B1/ko not_active IP Right Cessation
-
1990
- 1990-02-22 NL NL9000431A patent/NL194178C/nl not_active IP Right Cessation
- 1990-02-26 DE DE4005992A patent/DE4005992C2/de not_active Expired - Lifetime
- 1990-02-28 FR FR9002485A patent/FR2656726B1/fr not_active Expired - Lifetime
- 1990-02-28 GB GB9004448A patent/GB2239556B/en not_active Expired - Lifetime
- 1990-02-28 US US07/488,740 patent/US5155700A/en not_active Expired - Lifetime
- 1990-04-13 JP JP2096599A patent/JPH0783060B2/ja not_active Expired - Lifetime
- 1990-07-31 CN CN90106626A patent/CN1021997C/zh not_active Expired - Fee Related
- 1990-07-31 IT IT48189A patent/IT1241524B/it active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| GB2239556A (en) | 1991-07-03 |
| FR2656726B1 (fr) | 1995-02-03 |
| IT9048189A0 (it) | 1990-07-31 |
| KR910013262A (ko) | 1991-08-08 |
| NL9000431A (nl) | 1991-07-16 |
| GB2239556B (en) | 1993-08-25 |
| JPH0783060B2 (ja) | 1995-09-06 |
| KR930001737B1 (ko) | 1993-03-12 |
| IT9048189A1 (it) | 1992-01-31 |
| FR2656726A1 (fr) | 1991-07-05 |
| DE4005992A1 (de) | 1991-07-11 |
| NL194178C (nl) | 2001-08-03 |
| GB9004448D0 (en) | 1990-04-25 |
| JPH03203369A (ja) | 1991-09-05 |
| CN1021997C (zh) | 1993-09-01 |
| US5155700A (en) | 1992-10-13 |
| CN1052967A (zh) | 1991-07-10 |
| NL194178B (nl) | 2001-04-02 |
| DE4005992C2 (de) | 1994-01-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted | ||
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970528 |