US6327170B1 - Reducing impact of coupling noise in multi-level bitline architecture - Google Patents
Reducing impact of coupling noise in multi-level bitline architecture Download PDFInfo
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- US6327170B1 US6327170B1 US09/406,890 US40689099A US6327170B1 US 6327170 B1 US6327170 B1 US 6327170B1 US 40689099 A US40689099 A US 40689099A US 6327170 B1 US6327170 B1 US 6327170B1
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- 238000010168 coupling process Methods 0.000 title claims abstract description 35
- 238000005859 coupling reaction Methods 0.000 title claims abstract description 35
- 230000015654 memory Effects 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 6
- 230000002411 adverse Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 6
- 230000007423 decrease Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
Definitions
- the present invention relates generally to reducing the adverse impact of noise coupling in signal lines of, for example, an integrated circuit (IC).
- the invention relates to bitline architectures which reduce the impact of noise to improve sensing of memory cells.
- a conventional dynamic random access memory cell 101 is shown.
- the memory cell comprises a cell transistor 110 and a cell capacitor 150 for storing information.
- a first junction 111 of the transistor is coupled to a bitline 125
- a second junction 112 is coupled to the capacitor 150 .
- a gate electrode 113 of the transistor is coupled to a wordline 126 .
- a reference or constant voltage (V pl ) can be coupled to a plate of the capacitor. The plate which is coupled to the reference voltage can serve as a common plate in the memory array.
- Bitlines are arranged in rows and columns to form an array, connected by wordlines in the row direction and bitlines in the column direction.
- the bitlines are coupled to sense amplifiers to facilitate memory accesses.
- a pair of bitlines is coupled to a sense amplifier.
- the bitline containing the selected memory cell is referred to as the bitline or bitline true and the other is referred to as the reference bitline or bitline complement.
- bitlines can be arranged in various types of bitline architectures, such as open, folded, open-folded, diagonal, multi-level, split-level, or split-level diagonal.
- Multi-level or split-level bitline architectures are described in, for example, Hamada et al., A Split Level Diagonal Bitline Stack Capacitor Cell for 256 Mb DRAMs, IEDM 92-7990, which is herein incorporated by reference for all purposes.
- FIG. 2 shows a multi-level bitline architecture with vertical twists.
- a bitline pair 210 comprises bitlines 211 and 212 which occupy top and bottom bitline levels 230 and 220 .
- the bitlines are vertically aligned with each other in the different bitline levels. Twists 280 are provided to switch the positions of the bitlines from the top to the bottom bitline level.
- the bitline segments occupying the bottom level comprise memory cells 250 coupled thereto.
- a memory access typically comprises precharging the bitlines to a predefined voltage level (e.g., equalization voltage or V bleq ).
- a memory cell within a bitline pair is selected after the bitlines are precharged and floated.
- the memory cell is selected by rendering the transistor of the memory cell conductive, coupling the memory cell's capacitor to the bitline true. Depending on the value stored in the capacitor, the bitline true is pulled above or below V bleq .
- the reference bitline in the ideal case, remains at V bleq .
- the voltage difference between the reference bitline and bitline true is the differential voltage.
- a sense amplifier coupled to the bitline pair senses and amplifies the differential voltage signal, which is indicative of the data stored in the selected memory cell.
- differential signal i.e., differential voltage
- the differential signal sensed by a sense amplifier in an ideal situation, depends on the charge sharing between the bitline and the memory cell. The ratio of the bitline capacitance (and the capacitance of the sense amplifier) to the cell capacitance determines the magnitude of the differential signal.
- the voltage of the reference bitline increases or decreases along with the voltage swing on the bitline true due to bitline coupling between the bitlines of the bitline pair (intra-bitline coupling), thereby decreasing the magnitude of the differential signal or signal margin.
- substantial coupling noise between the reference bitline in the upper level and the bitline in the lower level in the vertical twisted multi-level bitline architecture causes a decrease in the signal margin of the differential signal.
- a reduction in the signal margin of the differential signal is undesirable as this may lead to incorrect evaluation of the data stored in the memory cell.
- coupling noise from neighboring bitline pairs can also reduce the signal margin.
- the sense amplifiers of the array may not be activated simultaneously. This occurs as a result of, for example, different amplification speeds for a “0” and a “1”, difference in the threshold voltage of the various latch transistors, or a skew in the activation of the sense amplifiers in the top and bottom bank in an interleaved arrangement.
- Coupling noise from a bitline pair whose differential signal is amplified can reduce the differential signal of a neighboring bitline pair whose differential signal has yet to be amplified.
- a memory IC comprises first and second bitline pairs in which the bitline paths of a bitline pair are on different bitline levels.
- the bitline paths of the different bitline pairs on different bitline levels are adjacent to each other.
- the first bitline pair comprises m vertical-horizontal twists, where m is a whole number ⁇ 1.
- the second bitline pair comprises n vertical-horizontal twists, where n is a whole number not equal to m.
- the vertical-horizontal twists switch the bitline paths of the bitlines within the bitline pair.
- the vertical-horizontal twists are provided along the bitline pairs to transform coupling noise between neighboring bitline pairs into common mode noise. Common mode noise is desirable since it does not reduce the signal margin of the differential signal.
- FIG. 1 shows a memory cell
- FIG. 2 shows a multi-level bitline architecture with vertical twists
- FIGS. 3-5 show embodiments of the invention for reducing the impact of coupling noise in signal lines.
- the invention relates generally to reducing the adverse impact of coupling noise in signal lines.
- the invention reduces the impact of coupling noise in bitlines of ICs such as, for example, random access memories (RAMs) including dynamic RAMs (DRAMs), high speed DRAMs such as Rambus DRAMs and SLDRAMs, ferroelectric RAMs (FRAMs), synchronous DRAMs (SDRAMs), merged DRAM-logic chips (embedded DRAMs), or other types of memory ICs or logic ICs.
- RAMs random access memories
- DRAMs dynamic RAMs
- high speed DRAMs such as Rambus DRAMs and SLDRAMs
- FRAMs ferroelectric RAMs
- SDRAMs synchronous DRAMs
- merged DRAM-logic chips embedded DRAMs
- FIG. 3 shows a plan view of one embodiment of the invention for reducing the adverse impact of coupling noise.
- First signal line pair 310 (bolded lines) and second signal line pair 320 (unbolded lines) are provided.
- the signal line pairs comprises signal lines, which, for example, can be differential signal lines, internal differential data lines, differential clock lines, or other types of differential signal lines in an IC.
- the signal line pairs comprise bitline pairs.
- bitline solid line
- reference bitline dotted line
- the bitlines of a bitline pair occupy bitline paths that are on different horizontal and vertical planes. That is, the bitline paths of a bitline pair are on different bitline levels and are not vertically aligned on the different bitline levels.
- the different bitline levels can be realized in, for example, metal 0 (MO) and metal 1 (M 1 )of the IC.
- the first bitline pair comprises bitlines 311 and 312 occupying bitline paths 311 p and 312 p .
- bitline path 311 p is located on a second bitline level while bitline path 312 p is on a first bitline level.
- the first bitline level for example, is the upper bitline level and the second bitline level is the lower bitline level.
- the bitline paths are not substantially aligned with each other on the different bitline levels.
- the second bitline pair comprises bitlines 321 and 322 that occupy bitline paths 321 p and 322 p .
- bitline paths 321 p and 322 p are on different bitline levels (first and second, respectively) and are not substantially vertically aligned with each other.
- a bitline path of one bitline pair is adjacent to a bitline path of the other bitline pair on different bitline levels.
- a bitline path of one bitline pair is substantially vertically aligned with a bitline path of the other bitline pair.
- Memory cells are, for example, coupled to bitline segments in the lower bitline level. Providing bitline paths of one bitline pair which are offset with respect to bitline paths of another bitline pair can also be useful, for example, to facilitate coupling of memory cells to the bitlines on different bitline levels.
- bitline path of the first bitline pair is adjacent to a bitline path of the second bitline pair on the same bitline level. Interleaving one or more bitline paths from other bitline pairs between the bitline paths of the first and second bitline pairs is also useful.
- m twists are provided in one of the bitline pairs, where m is a whole number ⁇ 1.
- a twist switches the bitline paths of the bitlines within the bitline pair. Since the bitline paths of the bitline pair are not on the same bitline level and are not vertically aligned with each other, the twist changes the vertical and horizontal positions of the bitlines within the bitline pair. As such, the twist is referred to as a vertical-horizontal (v-h) twist.
- the other bitline pair can be provided with n v-h twists, where n is a whole number not equal to m.
- the twists separate the bitlines into a plurality of bitline segments (m+1 or n+1 if n>0).
- the first and second bitline pairs comprise a different number of segments since each contains a different number of twists.
- the total lengths of the first and second bitline segments in a bitline path are about equal.
- the twist or twists are placed such that the bitlines from one bitline pair and the bitlines from the other bitline pair impact each other in the same manner.
- coupling noise between the bitline pairs is transformed into common mode noise, which does not adversely impact the signal margin of the differential signal between the bitlines of a bitline pair.
- the v-h twist is located at about the middle of the bitline pair, separating the bitlines 311 and 322 into bitline segments 311 a-b and reference bitline segments 312 a-b of about ⁇ fraction (1/2+L ) ⁇ the length of a bitline.
- the v-h twist switches the vertical and horizontal positions of the bitlines within the bitline pair (i.e., changes the bitline paths of the bitlines).
- bitline 311 occupies bitline path 311 p which is located on the lower level and reference bitline 312 (segment 312 a ) occupies bitline path 312 p on the upper bitline level.
- bitline (segment 311 b ) and reference bitline (segment 312 b ) to the right of twist 340 now occupy bitline paths 312 p and 311 p , respectively, switching the paths of the bitlines within the bitline pair.
- most of the various coupling noise components are transferred into common mode noise which is advantageous since common mode noise does not decrease the magnitude of the differential signal.
- FIG. 4 shows another embodiment of the invention for reducing the impact of coupling noise.
- v-h twists are provided in first and second bitline pairs 410 and 420 .
- bitline pair 420 comprises v-h twists 460 and 461
- bitline pair 410 comprises v-h twist 440 . Twists 460 and 461 separate bitlines of the bitline pair 420 into segments 421 a-c and segments 422 a-c .
- Bitline segments 421 a , 421 c , 422 a , and 422 c are each about ⁇ fraction (1/4+L ) ⁇ the length of a bitline and segments 421 b and 422 b are each about ⁇ fraction (1/2+L ) ⁇ the length of a bitline.
- Twist 440 separates bitlines of the bitline pair 410 into segments 411 a-b and 412 a-b , each being about ⁇ fraction (1/2+L ) ⁇ the length of a bitline. The twists alter the vertical and horizontal positions of the bitlines within the bitline pairs.
- the twists of a bitline pair separates the bitlines into segments of a predefined length such that the total lengths of the first and second bitline segments along a bitline path are about equal.
- the twists are located along the bitline pairs to transform coupling noise between the bitline pairs into common mode noise.
- FIG. 5 shows yet another embodiment of the invention for reducing the impact of coupling noise.
- v-h twists are provided in first and second bitline pairs 510 and 520 .
- Bitline pair 520 is provided with v-h twists 560 - 562 and bitline pair 510 is provided with a v-h twist 540 .
- the twists 560 - 562 divide the bitlines into segments 521 a-d and 522 a-d , each about ⁇ fraction (1/4+L ) ⁇ the length of a bitline.
- the twist 540 divides the bitlines of the bitline pair 510 into segments 511 a-b and 512 a-b , each being about ⁇ fraction (1/2+L ) ⁇ the length of a bitline.
- the twists alter the vertical and horizontal positions of the bitlines within the bitline pairs in order to cause coupling noise between the bitline pairs to be common mode noise.
- FIG. 6 shows a plan view of an array 600 in accordance with one embodiment of the inventions.
- the array includes a plurality of building blocks 601 which comprise first and second bitline pairs 410 and 420 .
- the building blocks are repeatedly placed adjacent to other building blocks to form the array.
- the building blocks used are similar to the first and second bitline pairs described in FIG. 4 .
- the use of building blocks such as those described in FIG. 3, FIG. 5, or other configurations are also useful to reduce the impact of coupling noise. It is not necessary to configure all building blocks in the array with the same m and n values.
- interleaving building blocks together can be useful. Interleaving building blocks results in bitline paths of a building block being adjacent to bitline paths from another building block. In one embodiment, the building blocks are interleaved together such that the bitline paths of a building block are not adjacent to each other. Providing an array with a variety of different types of building blocks, such as building blocks with vertical twists as described in FIG.
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Abstract
Description
Claims (23)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/406,890 US6327170B1 (en) | 1999-09-28 | 1999-09-28 | Reducing impact of coupling noise in multi-level bitline architecture |
PCT/US2000/024918 WO2001024188A1 (en) | 1999-09-28 | 2000-09-12 | Arrangement to reduce coupling noise between bitlines |
KR1020027004037A KR100849267B1 (en) | 1999-09-28 | 2000-09-12 | Arrangement to reduce coupling noise between bitlines |
DE60028392T DE60028392T2 (en) | 1999-09-28 | 2000-09-12 | ARRANGEMENT FOR REDUCING COUPLING INTERFERENCE BETWEEN BIT HEADS |
EP00961805A EP1216478B1 (en) | 1999-09-28 | 2000-09-12 | Arrangement to reduce coupling noise between bitlines |
JP2001527288A JP2003510753A (en) | 1999-09-28 | 2000-09-12 | Architecture to reduce coupling noise between bit lines |
TW089119638A TW475176B (en) | 1999-09-28 | 2000-09-22 | Reducing impact of coupling noise in multilevel bitline architecture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US09/406,890 US6327170B1 (en) | 1999-09-28 | 1999-09-28 | Reducing impact of coupling noise in multi-level bitline architecture |
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US6327170B1 true US6327170B1 (en) | 2001-12-04 |
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US09/406,890 Expired - Lifetime US6327170B1 (en) | 1999-09-28 | 1999-09-28 | Reducing impact of coupling noise in multi-level bitline architecture |
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US (1) | US6327170B1 (en) |
EP (1) | EP1216478B1 (en) |
JP (1) | JP2003510753A (en) |
KR (1) | KR100849267B1 (en) |
DE (1) | DE60028392T2 (en) |
TW (1) | TW475176B (en) |
WO (1) | WO2001024188A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6430076B1 (en) * | 2001-09-26 | 2002-08-06 | Infineon Technologies Ag | Multi-level signal lines with vertical twists |
US20070226673A1 (en) * | 2006-03-27 | 2007-09-27 | Habitz Peter A | Method of reducing correclated coupling between nets |
US20090189708A1 (en) * | 2008-01-25 | 2009-07-30 | Micron Technology, Inc, | Coupling cancellation scheme |
US20090307647A1 (en) * | 2008-06-10 | 2009-12-10 | Kabushiki Kaisha Toshiba | Layout design method and computer-readable medium |
US20140133231A1 (en) * | 2012-11-15 | 2014-05-15 | SanDisk Technologies, Inc. | Bit line resistance compensation |
Citations (1)
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US5999480A (en) * | 1995-04-05 | 1999-12-07 | Micron Technology, Inc. | Dynamic random-access memory having a hierarchical data path |
Family Cites Families (11)
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JPS63108593A (en) * | 1986-10-27 | 1988-05-13 | Fujitsu Ltd | Dynamic random access memory |
JPS63183691A (en) * | 1987-01-26 | 1988-07-29 | Mitsubishi Electric Corp | Semiconductor storage device |
JPH0766657B2 (en) * | 1988-05-11 | 1995-07-19 | 三菱電機株式会社 | Semiconductor memory device |
US5144583A (en) * | 1989-01-09 | 1992-09-01 | Kabushiki Kaisha Toshiba | Dynamic semiconductor memory device with twisted bit-line structure |
KR930001737B1 (en) * | 1989-12-29 | 1993-03-12 | 삼성전자 주식회사 | Wordline array method of semiconductor memory device |
FR2668640A1 (en) * | 1990-10-30 | 1992-04-30 | Samsung Electronics Co Ltd | Semiconductor memory possessing bit lines and word lines which cross over |
US5864181A (en) | 1993-09-15 | 1999-01-26 | Micron Technology, Inc. | Bi-level digit line architecture for high density DRAMs |
JP3354230B2 (en) * | 1993-09-21 | 2002-12-09 | 株式会社東芝 | Dynamic semiconductor memory device |
WO1997028532A1 (en) * | 1996-02-01 | 1997-08-07 | Micron Technology, Inc. | Digit line architecture for dynamic memory |
US6018480A (en) * | 1998-04-08 | 2000-01-25 | Lsi Logic Corporation | Method and system which permits logic signal routing over on-chip memories |
KR100300047B1 (en) * | 1998-05-30 | 2001-09-22 | 김영환 | Semicondcutor device with data line arrangement for preventing of noise interference |
-
1999
- 1999-09-28 US US09/406,890 patent/US6327170B1/en not_active Expired - Lifetime
-
2000
- 2000-09-12 KR KR1020027004037A patent/KR100849267B1/en not_active IP Right Cessation
- 2000-09-12 JP JP2001527288A patent/JP2003510753A/en active Pending
- 2000-09-12 EP EP00961805A patent/EP1216478B1/en not_active Expired - Lifetime
- 2000-09-12 DE DE60028392T patent/DE60028392T2/en not_active Expired - Fee Related
- 2000-09-12 WO PCT/US2000/024918 patent/WO2001024188A1/en active IP Right Grant
- 2000-09-22 TW TW089119638A patent/TW475176B/en not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US5999480A (en) * | 1995-04-05 | 1999-12-07 | Micron Technology, Inc. | Dynamic random-access memory having a hierarchical data path |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6430076B1 (en) * | 2001-09-26 | 2002-08-06 | Infineon Technologies Ag | Multi-level signal lines with vertical twists |
US20070226673A1 (en) * | 2006-03-27 | 2007-09-27 | Habitz Peter A | Method of reducing correclated coupling between nets |
US7464359B2 (en) | 2006-03-27 | 2008-12-09 | International Business Machines Corporation | Method for re-routing an interconnection array to improve switching behavior in a single net and an associated interconnection array structure |
US20090189708A1 (en) * | 2008-01-25 | 2009-07-30 | Micron Technology, Inc, | Coupling cancellation scheme |
US7830221B2 (en) | 2008-01-25 | 2010-11-09 | Micron Technology, Inc. | Coupling cancellation scheme |
US20110025428A1 (en) * | 2008-01-25 | 2011-02-03 | Micron Technology, Inc. | Coupling cancellation scheme |
US8143966B2 (en) | 2008-01-25 | 2012-03-27 | Micron Technology, Inc. | Coupling cancellation scheme |
US20090307647A1 (en) * | 2008-06-10 | 2009-12-10 | Kabushiki Kaisha Toshiba | Layout design method and computer-readable medium |
US20140133231A1 (en) * | 2012-11-15 | 2014-05-15 | SanDisk Technologies, Inc. | Bit line resistance compensation |
US8988917B2 (en) * | 2012-11-15 | 2015-03-24 | Sandisk Technologies Inc. | Bit line resistance compensation |
Also Published As
Publication number | Publication date |
---|---|
JP2003510753A (en) | 2003-03-18 |
WO2001024188A1 (en) | 2001-04-05 |
KR20030009302A (en) | 2003-01-29 |
EP1216478B1 (en) | 2006-05-31 |
DE60028392D1 (en) | 2006-07-06 |
EP1216478A1 (en) | 2002-06-26 |
DE60028392T2 (en) | 2007-06-06 |
KR100849267B1 (en) | 2008-07-29 |
TW475176B (en) | 2002-02-01 |
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