KR910007096A - Tab 테이프와 반도체 칩을 접속하는 방법 및 그것에 사용하는 범프시이트와 범프부착 tab 테이프 - Google Patents

Tab 테이프와 반도체 칩을 접속하는 방법 및 그것에 사용하는 범프시이트와 범프부착 tab 테이프 Download PDF

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KR910007096A
KR910007096A KR1019900014073A KR900014073A KR910007096A KR 910007096 A KR910007096 A KR 910007096A KR 1019900014073 A KR1019900014073 A KR 1019900014073A KR 900014073 A KR900014073 A KR 900014073A KR 910007096 A KR910007096 A KR 910007096A
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semiconductor chip
bump
bumps
tab tape
fixed
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KR1019900014073A
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KR940004246B1 (ko
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야스히데 오노
다다까쓰 마루야마
히로 야끼 오쓰까
히로유끼 다나하시
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사이또오 히로시
신닛뽕 세이데쓰 가부시끼가이샤
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Priority claimed from JP1234916A external-priority patent/JP2780376B2/ja
Priority claimed from JP1234915A external-priority patent/JP2780375B2/ja
Application filed by 사이또오 히로시, 신닛뽕 세이데쓰 가부시끼가이샤 filed Critical 사이또오 히로시
Publication of KR910007096A publication Critical patent/KR910007096A/ko
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Publication of KR940004246B1 publication Critical patent/KR940004246B1/ko

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    • H—ELECTRICITY
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    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/79—Apparatus for Tape Automated Bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract

내용 없음

Description

TAB 테이프와 반도체 칩을 접속하는 방법 및 그것에 사용하는 범프시이트와 범프부착 TAB 테이프
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 TAB테이프와 반도체칩을 접촉하는 방법의 일실시예를 나타낸 도면.
제1A도는 제1도의 방법에 사용하는 범프시이트의 사시도.

Claims (8)

  1. 미리 접속코저하는 반도체 칩의 전극패턴(7)에 대응하는 위치에 보올상 범프(6)을 배열하여 고정하는 것과, 전기한 반도체 칩의 각 전극(7)이 전기한 TAB테이프(12)의 대응하는 리이드(2)와 전기한 범프(6)을 개재하여 전기적으로 접속되도록 전가한 각 범프를 전기한 반도체 칩의 대응전극 및 전기한 TAB테이프의 대응하는 리이드에 열압착하는 것을 특징으로 하는 TAB테이프(12)와 반도체칩(1)을 접속하는 방법.
  2. 제1항에 있어서, 전기한 범프는 합성수지 필름의 기판상(22)에 전기한 접속코저하는 반도체 칩의 전극패턴에 대응하는 위치에 배열되며, 고정됨을 특징으로 하는 방법.
  3. 제1항에 있어서, 전기한 범프는 합성수지 필름의 기판상에 전기한 접속코저하는 반도체 칩의 전극패턴에 대응하는 위치에 전기한 범프를 배열한 범프시이트에서 전기한 범프를 접속코저하는 TAB테이프(12)의 전기한 리이드(2)의 전기한 반도체 칩 전극에 접속해야할 부분에 전사하여 고정됨을 특징으로 하는 방법.
  4. 제1항에 있어서, 전기한 범프는 합성수지 필름의 기판위에 전기한 접속코저하는 반도체 칩의 전극패턴에 대응하는 위치에 전기한 범프를 배열한 범프시이트의 형태로 고정되며, 전기한 접속코저하는TAB테이프의 리이드는 전기한 범프시이트의 전기한 합성수지 필음의 한쪽 면상에 전기한 범프와 전기적으로 도통하도록 소정패턴으로 형성됨을 특징으로 하는 방법.
  5. 합성수지의 기판(22)과, 전기한 기판상의 접속코저하는 반도체 칩의 전극 배열에 대응하는 위치에 고정된 금속제의 보올상의 범프(6)가 TAB테이프(12)와 반도체 칩(1)을 접속하는 방법에 사용됨을 특징으로 하는 범프시이트.
  6. 제5항에 있어서, 전기한 범프는 전기한 합성수지 피름의 양면에 돌기하도록 고정됨을 특징으로 하는 범프시이트.
  7. 접속코저하는 반도체 칩의 전극 배열에 대응하는 배열을 가진 리이드(2)를 갖춘 합성수지의 TAB테이프(12)와, 전기한 리이드의 각 단부에 고착된 금속제의 범프(6)로 하여금, 전기한 각 리이드가 대응하는 전기한 반도체의 칩과 전기한 범프를 개재하여 접속될때, 전기한 반도체 칩에 접속되는 전기한 범프의 부분은 적어도 그 형상이 대략 보올상의 일부를 형성함을 특징으로 하는 범프부착 TAB테이프.
  8. 제 7항에 있어서, 전기한 범프는 전기한 TAB테이프의 양단에 돌출하도록 고정됨을 특징으로 하는 범프 부착 TAB테이프.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900014073A 1989-09-11 1990-09-06 Tab 테이프와 반도체칩을 접속하는 방법 및 그것에 사용하는 범프시이트와 범프 부착 tab 테이프 KR940004246B1 (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP1234916A JP2780376B2 (ja) 1989-09-11 1989-09-11 バンプ付きｔａｂテープの製造方法
JP1234915A JP2780375B2 (ja) 1989-09-11 1989-09-11 Ｔａｂテープと半導体チップを接続する方法およびそれに用いるバンプシート
JP01-234915 1989-09-11
JP01-234916 1989-09-11
JP23491789 1989-09-11
JP01-234917 1989-09-11

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KR910007096A true KR910007096A (ko) 1991-04-30
KR940004246B1 KR940004246B1 (ko) 1994-05-19

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US (1) US5164336A (ko)
EP (3) EP0427384B1 (ko)
KR (1) KR940004246B1 (ko)
DE (2) DE69027448T2 (ko)
MY (1) MY106847A (ko)
SG (1) SG73389A1 (ko)

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Publication number Publication date
DE69027448D1 (de) 1996-07-18
EP0911873A3 (en) 1999-12-15
EP0527387A1 (en) 1993-02-17
EP0427384A3 (en) 1992-01-02
DE69033078T2 (de) 1999-12-23
EP0911873A2 (en) 1999-04-28
MY106847A (en) 1995-08-30
DE69027448T2 (de) 1996-10-10
EP0427384B1 (en) 1999-04-28
DE69033078D1 (de) 1999-06-02
US5164336A (en) 1992-11-17
SG73389A1 (en) 2000-06-20
EP0427384A2 (en) 1991-05-15
KR940004246B1 (ko) 1994-05-19
EP0527387B1 (en) 1996-06-12

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