KR910002236B1 - 반도체집적회로장치 - Google Patents

반도체집적회로장치 Download PDF

Info

Publication number
KR910002236B1
KR910002236B1 KR1019870008021A KR870008021A KR910002236B1 KR 910002236 B1 KR910002236 B1 KR 910002236B1 KR 1019870008021 A KR1019870008021 A KR 1019870008021A KR 870008021 A KR870008021 A KR 870008021A KR 910002236 B1 KR910002236 B1 KR 910002236B1
Authority
KR
South Korea
Prior art keywords
circuit
test
scan
data
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
KR1019870008021A
Other languages
English (en)
Korean (ko)
Other versions
KR880014475A (ko
Inventor
이찌로오 도미오까
도시아끼 하니부찌
사도루 기시다
가즈히로 사까시다
다까히고 아라가와
Original Assignee
미쓰비시 뎅기 가부시끼가이샤
시기모리야
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP61183686A external-priority patent/JPH0627777B2/ja
Priority claimed from JP61183683A external-priority patent/JPH0627775B2/ja
Priority claimed from JP61183688A external-priority patent/JPH0627779B2/ja
Application filed by 미쓰비시 뎅기 가부시끼가이샤, 시기모리야 filed Critical 미쓰비시 뎅기 가부시끼가이샤
Publication of KR880014475A publication Critical patent/KR880014475A/ko
Application granted granted Critical
Publication of KR910002236B1 publication Critical patent/KR910002236B1/ko
Expired legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1019870008021A 1986-08-04 1987-07-23 반도체집적회로장치 Expired KR910002236B1 (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP61-183683 1986-08-04
JP61183686A JPH0627777B2 (ja) 1986-08-04 1986-08-04 半導体集積回路装置
JP61183683A JPH0627775B2 (ja) 1986-08-04 1986-08-04 半導体集積回路装置
JP61183688A JPH0627779B2 (ja) 1986-08-04 1986-08-04 半導体集積回路装置
JP61-183686 1986-08-04
JP61-183688 1986-08-04

Publications (2)

Publication Number Publication Date
KR880014475A KR880014475A (ko) 1988-12-24
KR910002236B1 true KR910002236B1 (ko) 1991-04-08

Family

ID=27325320

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870008021A Expired KR910002236B1 (ko) 1986-08-04 1987-07-23 반도체집적회로장치

Country Status (3)

Country Link
US (1) US4870345A (enExample)
KR (1) KR910002236B1 (enExample)
DE (1) DE3725823A1 (enExample)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6304987B1 (en) 1995-06-07 2001-10-16 Texas Instruments Incorporated Integrated test circuit
EP0358365B1 (en) * 1988-09-07 1998-10-21 Texas Instruments Incorporated Testing buffer/register
NL8900151A (nl) * 1989-01-23 1990-08-16 Philips Nv Werkwijze voor het testen van een schakeling, alsmede schakeling geschikt voor een dergelijke werkwijze.
US5483518A (en) 1992-06-17 1996-01-09 Texas Instruments Incorporated Addressable shadow port and protocol for serial bus networks
JP3005250B2 (ja) 1989-06-30 2000-01-31 テキサス インスツルメンツ インコーポレイテツド バスモニター集積回路
JP2626920B2 (ja) * 1990-01-23 1997-07-02 三菱電機株式会社 スキャンテスト回路およびそれを用いた半導体集積回路装置
US6675333B1 (en) 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
JP2567972B2 (ja) * 1990-06-06 1996-12-25 富士通株式会社 フリップフロップ回路及び半導体集積回路
JPH0474977A (ja) * 1990-07-16 1992-03-10 Nec Corp 半導体集積回路
JP2535670B2 (ja) * 1991-01-28 1996-09-18 株式会社東芝 双方向入出力端子用バウンダリスキャンセル
JP2770617B2 (ja) * 1991-09-05 1998-07-02 日本電気株式会社 テスト回路
GR920100088A (el) * 1992-03-05 1993-11-30 Consulting R & D Corp Koloni S Διαφανής έλεγχος ολοκληρωμένων κυκλωμάτων.
US5388225A (en) * 1992-09-16 1995-02-07 Texas Instruments Incorporated Time-domain boundary bridge method and apparatus for asynchronous sequential machines
DE69317221T2 (de) * 1992-11-24 1998-10-01 Advanced Micro Devices Inc Abtastprüfung für integrierte Schaltungen
US5420874A (en) * 1993-04-20 1995-05-30 Advanced Micro Devices, Inc. Testing of electrical circuits
JPH0764817A (ja) * 1993-08-30 1995-03-10 Mitsubishi Electric Corp 故障検出システム
US5528601A (en) * 1994-09-16 1996-06-18 International Business Machines Corporation Scannable latch for multiplexor control
JP2953975B2 (ja) * 1995-02-09 1999-09-27 日本電気アイシーマイコンシステム株式会社 テストパタン生成装置およびテストパタン生成方法
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US5958077A (en) * 1995-12-27 1999-09-28 Nec Usa, Inc. Method for testing asynchronous circuits
JPH1083698A (ja) * 1996-09-05 1998-03-31 Mitsubishi Electric Corp 半導体集積回路装置
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US7058862B2 (en) 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
JP2003509770A (ja) * 1999-09-10 2003-03-11 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ テスト命令メモリ付きマイクロコンピュータ
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
JP4150886B2 (ja) * 2002-04-19 2008-09-17 ソニー株式会社 暗号化復号化演算装置およびデータ受信装置
FR2840074A1 (fr) * 2002-05-22 2003-11-28 Koninkl Philips Electronics Nv Cellule de tension fixe pour circuit integre
AR040229A1 (es) * 2002-05-22 2005-03-23 Novartis Ag Amidoacetonitrilos
JP2004069642A (ja) * 2002-08-09 2004-03-04 Renesas Technology Corp 半導体集積回路装置
JP4279023B2 (ja) * 2003-03-25 2009-06-17 富士通株式会社 状態表示情報設定回路
US7153460B2 (en) * 2003-12-22 2006-12-26 Lear Corporation System and method for providing a renewable masking surface
US7453759B2 (en) * 2006-04-26 2008-11-18 International Business Machines Corporation Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5228614A (en) * 1975-08-30 1977-03-03 Kenkichi Suzuki Thyrister leonard
US4051352A (en) * 1976-06-30 1977-09-27 International Business Machines Corporation Level sensitive embedded array logic system
JPS54121036A (en) * 1978-03-13 1979-09-19 Cho Lsi Gijutsu Kenkyu Kumiai Method of testing function of logic circuit
US4244048A (en) * 1978-12-29 1981-01-06 International Business Machines Corporation Chip and wafer configuration and testing method for large-scale-integrated circuits
JPS5674668A (en) * 1979-11-22 1981-06-20 Nec Corp Logical device
DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
US4493077A (en) * 1982-09-09 1985-01-08 At&T Laboratories Scan testable integrated circuit
US4513418A (en) * 1982-11-08 1985-04-23 International Business Machines Corporation Simultaneous self-testing system
US4580137A (en) * 1983-08-29 1986-04-01 International Business Machines Corporation LSSD-testable D-type edge-trigger-operable latch with overriding set/reset asynchronous control
US4554664A (en) * 1983-10-06 1985-11-19 Sperry Corporation Static memory cell with dynamic scan test latch
DE3373729D1 (en) * 1983-12-08 1987-10-22 Ibm Deutschland Testing and diagnostic device for a digital calculator
JPH0772744B2 (ja) * 1984-09-04 1995-08-02 株式会社日立製作所 半導体集積回路装置
US4703257A (en) * 1984-12-24 1987-10-27 Hitachi, Ltd. Logic circuit having a test data scan circuit
US4698588A (en) * 1985-10-23 1987-10-06 Texas Instruments Incorporated Transparent shift register latch for isolating peripheral ports during scan testing of a logic circuit
US4752729A (en) * 1986-07-01 1988-06-21 Texas Instruments Incorporated Test circuit for VSLI integrated circuits

Also Published As

Publication number Publication date
DE3725823A1 (de) 1988-02-18
DE3725823C2 (enExample) 1990-08-09
US4870345A (en) 1989-09-26
KR880014475A (ko) 1988-12-24

Similar Documents

Publication Publication Date Title
KR910002236B1 (ko) 반도체집적회로장치
KR900002770B1 (ko) 반도체 집적회로장치
US5130568A (en) Scannable latch system and method
US4493077A (en) Scan testable integrated circuit
JP2725258B2 (ja) 集積回路装置
US5349587A (en) Multiple clock rate test apparatus for testing digital systems
US6115827A (en) Clock skew management method and apparatus
KR100214239B1 (ko) 부분 스캔 패스 회로를 갖는 집적 논리 회로와 부분 스캔 패스 설계 방법
JP2626920B2 (ja) スキャンテスト回路およびそれを用いた半導体集積回路装置
KR900002444B1 (ko) 반도체 집적회로장치
EP0136461A1 (en) Level sensitive scan design testable latch circuit apparatus
EP1034479B1 (en) TEST CIRCUITRY FOR ASICs
US5530706A (en) Non-destructive sampling of internal states while operating at normal frequency
EP0289158A2 (en) Diagnostic apparatus for a data processing system
EP0633530B1 (en) Testing sequential logic circuit upon changing into combinatorial logic circuit
US6065145A (en) Method for testing path delay faults in sequential logic circuits
KR910000608B1 (ko) 반도체 집적회로장치
US5471152A (en) Storage element for delay testing
US5068881A (en) Scannable register with delay test capability
KR100582807B1 (ko) 아날로그 회로 및 디지털 회로를 구비하는 검사 가능한 집적 회로
US4682329A (en) Test system providing testing sites for logic circuits
JP2953435B2 (ja) 遅延テスト方法および該遅延テスト方法に使用するフリップフロップ
JPH09243705A (ja) 半導体論理集積回路
US6272656B1 (en) Semiconductor integrated circuit including test facilitation circuit and test method thereof
JPH0627775B2 (ja) 半導体集積回路装置

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19870723

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19870723

Comment text: Request for Examination of Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19900629

Patent event code: PE09021S01D

G160 Decision to publish patent application
PG1605 Publication of application before grant of patent

Comment text: Decision on Publication of Application

Patent event code: PG16051S01I

Patent event date: 19910309

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19910625

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19910701

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19910701

End annual number: 3

Start annual number: 1

PR1001 Payment of annual fee

Payment date: 19940319

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 19950403

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 19960327

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 19970401

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 19980331

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 19990330

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20000328

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20010328

Start annual number: 11

End annual number: 11

PR1001 Payment of annual fee

Payment date: 20020403

Start annual number: 12

End annual number: 12

PR1001 Payment of annual fee

Payment date: 20030320

Start annual number: 13

End annual number: 13

PR1001 Payment of annual fee

Payment date: 20040323

Start annual number: 14

End annual number: 14

PR1001 Payment of annual fee

Payment date: 20050322

Start annual number: 15

End annual number: 15

FPAY Annual fee payment

Payment date: 20060327

Year of fee payment: 16

PR1001 Payment of annual fee

Payment date: 20060327

Start annual number: 16

End annual number: 16

EXPY Expiration of term
PC1801 Expiration of term