GR920100088A - Διαφανής έλεγχος ολοκληρωμένων κυκλωμάτων. - Google Patents
Διαφανής έλεγχος ολοκληρωμένων κυκλωμάτων.Info
- Publication number
- GR920100088A GR920100088A GR920100088A GR920100088A GR920100088A GR 920100088 A GR920100088 A GR 920100088A GR 920100088 A GR920100088 A GR 920100088A GR 920100088 A GR920100088 A GR 920100088A GR 920100088 A GR920100088 A GR 920100088A
- Authority
- GR
- Greece
- Prior art keywords
- registers
- integrated circuits
- test
- ram
- input
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318522—Test of Sequential circuits
- G01R31/318527—Test of counters
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/27—Built-in tests
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/32—Serial access; Scan testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/40—Response verification devices using compression techniques
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/83—Indexing scheme relating to error detection, to error correction, and to monitoring the solution involving signatures
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Περιγράψαμε μία τεχνική γιά διαφανή έλεγχο ολοκληρωμένωνκυκλωμάτων. Επιτρέπει τον έλεγχο των ολοκληρωμένων κυκλωμάτωνχωρίς απώλεια της κατάστασης του προγράμματος εκτέλεσης μίαςεφαρμογής. Η τεχνική αυτή θεωρεί δυο είδη κυκλωμάτων,συνδιαστικά και ακολουθιακά κυκλώματα από τη μία μεριά, καιμνήμες RAM και μπλοκ καταχωρητών (register files) από τηνάλλη.Για το πρώτο είδος κυκλωμάτων προτείνουμε μία τεχνική τουτύπου διάσωση της κατάστασης, έλεγχος του κυκλώματος,αποκατάσταση της κατάστασης. Αυτη η τεχνική χρησιμοποιεί ένακυκλικό scan path για να μεταφέρει το περιεχόμενο διάφορωνκαταχωρητών μέχρι τις εισόδους δεδομένων μίας μνήμης,αποθηκεύει το περιεχόμενο αυτών των καταχωρητών στη μνήμη,εκτελεί τη φάση ελέγχου, φορτίζει τα αποθηκευμένα δεδομένααπό τη μνήμη στο scan path και τα μεταφέρει πίσω στουςκαταχωρητές.Για το δεύτερο είδος κυκλωμάτων προτείνουμε μία τεχνικήδιαφανούς ελέγχου που ελέγχει τις μνήμες χωρίς να καταστρέφειτο περιεχόμενο τους. Για το σκοπό αυτό προτείνουμε μία τεχνικήπου επιτρέπει την ανεύρεση διαδικασιών διαφανούς ελέγχουμνημών. Αυτές οι διαδικασίες ελέγχου μπορούν να εκτελεσθούνχρησιμοποιώντας τεχνικές κατασκευής για αυτοέλεγχο (BIST) ήτεχνικές δίαυλου προσπέλασης (scan path). Οι διαφανείςδιαδικασίες ελέγχου αποτελούνται από μία διαδικασία πρόβλεψηςυπογραφής προκύπτει εάν διαγράψουμε τις πράξεις εγγραφής και από μία βασική διαδικασία διαφανούς ελέγχου. Η διαδικασία πρόβλεψης υπογραφής προκύπτει εάν διαγράψουμε τις πράξεις εγγραφής από τη βασική διαδικασία διαφανούς ελέγχου. Οι πράξεις ανάγνωσης των οποίων τα δεδομένα δεν αποστέλονται στο κύκλωμα συμπίεσης δεδομένων εξόδου, μπορούν επίσης να διαγραφούν. Αυτη η τεχνική μας επιτρέπει να αποφύγουμε τη συγκάλυψη σφαλμάτων που μπορεί να προκύψει αν κάποια λάθη εμφανισθούν κατά τη διάρκεια της βασικής διαδικασίας διαφανούς ελέγχου και κατά τη διάρκεια της διαδικασίας πρόβλεψης υπογραφής. Η βασική διαδικασία διαφανούς ελέγχου μπορεί να παραχθεί από οποιαδήποτε κοινή (δηλαδή μη διαφανή) διαδικασία ελέγχου χρησιμοποιώντας ορισμένους μετασχηματισμούς. Αυτοί οιμετασχηματισμοί έχουν την ιδιότητα να μη μειώνουν την κάλυψησφαλμάτων όταν το μοντέλο επαληθεύει κάποια συμμετρικήιδιότητα. Η ιδιότητα αυτή επαληθεύεται από όλα σχεδόν ταγνωστά μοντέλα σφαλμάτων μνημών. Η διαφανής διαδικασίαελέγχου μνημών μπορεί επίσης να πραγματοποιηθείχρησιμοποιώντας μόνο τη βασική διαφανή διαδικασία ελέγχου.Αυτό είναι δυνατόν όταν η επαλήθευση των δεδομένων εξόδουπραγματοποιείται από ένα κώδικα ανεύρεσης λαθών (errordetecting code).Μία εναλλακτική λύση χρησιμοποιεί μία βοηθητική μνήμη στηνοποία αποθηκεύουμε ένα τμήμα της μνήμης κάθε φορά. Το τμήμααυτό της μνήμης ελέγχεται από μία διαφανή ή μία κοινήδιαδικασία ελέγχου. Στην περίπτωση της χρήσης κοινήςδιαδικασίας ελέγχου το περιεχόμενο του ελεγχθέντος τμήματοςαποκαθίστανται χρησιμοποιώντας το περιεχόμενο της βοηθητικήςμνήμης.Για διαφανή ή για κοινή κατασκευή για αυτοέλεγχο ένθετωνμνημών, προτείνουμε ένα κύκλωμα που διασυνδέεται: σαν Up/DownLFSR ώστε να παράγει τη σειρά διε
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GR92100088 | 1992-03-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
GR920100088A true GR920100088A (el) | 1993-11-30 |
Family
ID=10941053
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GR920100088A GR920100088A (el) | 1992-03-05 | 1992-03-05 | Διαφανής έλεγχος ολοκληρωμένων κυκλωμάτων. |
Country Status (6)
Country | Link |
---|---|
US (1) | US5469445A (el) |
EP (1) | EP0585435B1 (el) |
AT (1) | ATE198000T1 (el) |
DE (1) | DE69329720T2 (el) |
GR (1) | GR920100088A (el) |
WO (1) | WO1993018457A1 (el) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5528600A (en) | 1991-01-28 | 1996-06-18 | Actel Corporation | Testability circuits for logic arrays |
EP0599524A3 (en) * | 1992-11-24 | 1996-04-17 | Advanced Micro Devices Inc | Self-test for integrated storage networks. |
DE59603161D1 (de) * | 1995-03-10 | 1999-10-28 | Siemens Ag | Verfahren zur bestimmung einer zuverlässigkeits-kenngrösse eines responsiven systems sowie ein entsprechendes system zur signalverarbeitung |
KR0158610B1 (en) * | 1995-04-27 | 1998-12-15 | Samsung Electronics Co Ltd | Serial interface to memory using the interlaced scan |
EP0858630B1 (en) * | 1995-06-09 | 2005-03-23 | Fujitsu Limited | Method, system and apparatus for efficiently generating binary numbers for testing storage devices |
US5796751A (en) * | 1996-07-22 | 1998-08-18 | International Business Machines Corporation | Technique for sorting high frequency integrated circuits |
KR100238256B1 (ko) * | 1997-12-03 | 2000-01-15 | 윤종용 | 직접 억세스 모드 테스트를 사용하는 메모리 장치 및 테스트방법 |
KR100265760B1 (ko) * | 1997-12-03 | 2000-09-15 | 윤종용 | 직접엑세스모드테스트제어회로를구비하는고속반도체메모리장치및테스트방법 |
GB9802091D0 (en) | 1998-01-30 | 1998-03-25 | Sgs Thomson Microelectronics | Device scan testing |
US6321320B1 (en) * | 1998-10-30 | 2001-11-20 | Hewlett-Packard Company | Flexible and programmable BIST engine for on-chip memory array testing and characterization |
US6571363B1 (en) * | 1998-12-30 | 2003-05-27 | Texas Instruments Incorporated | Single event upset tolerant microprocessor architecture |
US6615392B1 (en) * | 2000-07-27 | 2003-09-02 | Logicvision, Inc. | Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby |
US7437531B2 (en) * | 2004-09-30 | 2008-10-14 | Intel Corporation | Testing memories |
EP1724788A1 (en) * | 2005-05-18 | 2006-11-22 | STMicroelectronics S.r.l. | Improved built-in self-test method and system |
US7840861B2 (en) * | 2006-06-27 | 2010-11-23 | Silicon Image, Inc. | Scan-based testing of devices implementing a test clock control structure (“TCCS”) |
US7793179B2 (en) | 2006-06-27 | 2010-09-07 | Silicon Image, Inc. | Test clock control structures to generate configurable test clocks for scan-based testing of electronic circuits using programmable test clock controllers |
GB2439968B (en) * | 2006-07-07 | 2011-05-25 | Advanced Risc Mach Ltd | Memory testing |
US20080209294A1 (en) * | 2007-02-26 | 2008-08-28 | Hakan Brink | Built-in self testing of a flash memory |
RU2455712C2 (ru) * | 2009-12-24 | 2012-07-10 | Государственное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" | Способ тестирования оперативных запоминающих устройств |
US8683307B2 (en) | 2011-05-27 | 2014-03-25 | International Business Machines Corporation | Checksum calculation, prediction and validation |
US8719752B1 (en) * | 2013-01-22 | 2014-05-06 | Lsi Corporation | Hierarchical crosstalk noise analysis model generation |
RU2660607C1 (ru) * | 2017-02-20 | 2018-07-06 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Воронежский государственный технический университет" | Способ тестирования оперативных запоминающих устройств |
US10408876B2 (en) * | 2018-01-29 | 2019-09-10 | Oracle International Corporation | Memory circuit march testing |
US11557365B2 (en) | 2019-08-16 | 2023-01-17 | Nxp B.V. | Combined ECC and transparent memory test for memory fault detection |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0240199A2 (en) * | 1986-03-31 | 1987-10-07 | Tandem Computers Incorporated | In-line scan control apparatus for data processor testing |
US4831623A (en) * | 1987-07-16 | 1989-05-16 | Raytheon Company | Swap scan testing of digital logic |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4687988A (en) * | 1985-06-24 | 1987-08-18 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
US5032783A (en) * | 1985-10-23 | 1991-07-16 | Texas Instruments Incorporated | Test circuit and scan tested logic device with isolated data lines during testing |
US4698588A (en) * | 1985-10-23 | 1987-10-06 | Texas Instruments Incorporated | Transparent shift register latch for isolating peripheral ports during scan testing of a logic circuit |
KR910002236B1 (ko) * | 1986-08-04 | 1991-04-08 | 미쓰비시 뎅기 가부시끼가이샤 | 반도체집적회로장치 |
JP2725258B2 (ja) * | 1987-09-25 | 1998-03-11 | 三菱電機株式会社 | 集積回路装置 |
US5155432A (en) * | 1987-10-07 | 1992-10-13 | Xilinx, Inc. | System for scan testing of logic circuit networks |
US5047710A (en) * | 1987-10-07 | 1991-09-10 | Xilinx, Inc. | System for scan testing of logic circuit networks |
US4929889A (en) * | 1988-06-13 | 1990-05-29 | Digital Equipment Corporation | Data path chip test architecture |
-
1992
- 1992-03-05 GR GR920100088A patent/GR920100088A/el unknown
-
1993
- 1993-03-05 AT AT93905586T patent/ATE198000T1/de not_active IP Right Cessation
- 1993-03-05 DE DE69329720T patent/DE69329720T2/de not_active Expired - Fee Related
- 1993-03-05 EP EP93905586A patent/EP0585435B1/en not_active Expired - Lifetime
- 1993-03-05 WO PCT/GR1993/000005 patent/WO1993018457A1/en active IP Right Grant
- 1993-11-04 US US08/140,156 patent/US5469445A/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0240199A2 (en) * | 1986-03-31 | 1987-10-07 | Tandem Computers Incorporated | In-line scan control apparatus for data processor testing |
US4831623A (en) * | 1987-07-16 | 1989-05-16 | Raytheon Company | Swap scan testing of digital logic |
Non-Patent Citations (2)
Title |
---|
PROCEEDINGS OF THE 24TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, 1987, pages 407-415 IEEE, New York, US; A. KRASNIEWSKI et al.: 'Circular self-test path: A low-cost BIST technique' * |
PROCEEDINGS OF THE IECI 1981, November 9- 12, 1981, pages144-148, IEEE, New York, US D.B. SCHOWENGERDT et al.:'Real time data non-destructive RAM self testing' * |
Also Published As
Publication number | Publication date |
---|---|
US5469445A (en) | 1995-11-21 |
DE69329720D1 (de) | 2001-01-11 |
ATE198000T1 (de) | 2000-12-15 |
WO1993018457A1 (en) | 1993-09-16 |
DE69329720T2 (de) | 2002-08-22 |
EP0585435B1 (en) | 2000-12-06 |
EP0585435A1 (en) | 1994-03-09 |
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