DE68928837T2 - Prüf-Puffer/Register - Google Patents

Prüf-Puffer/Register

Info

Publication number
DE68928837T2
DE68928837T2 DE68928837T DE68928837T DE68928837T2 DE 68928837 T2 DE68928837 T2 DE 68928837T2 DE 68928837 T DE68928837 T DE 68928837T DE 68928837 T DE68928837 T DE 68928837T DE 68928837 T2 DE68928837 T2 DE 68928837T2
Authority
DE
Germany
Prior art keywords
register
check buffer
check
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68928837T
Other languages
English (en)
Other versions
DE68928837D1 (de
Inventor
Lee D Whetsel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE68928837D1 publication Critical patent/DE68928837D1/de
Publication of DE68928837T2 publication Critical patent/DE68928837T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
DE68928837T 1988-09-07 1989-08-21 Prüf-Puffer/Register Expired - Fee Related DE68928837T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US24143988A 1988-09-07 1988-09-07

Publications (2)

Publication Number Publication Date
DE68928837D1 DE68928837D1 (de) 1998-11-26
DE68928837T2 true DE68928837T2 (de) 1999-05-12

Family

ID=22910707

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68928837T Expired - Fee Related DE68928837T2 (de) 1988-09-07 1989-08-21 Prüf-Puffer/Register

Country Status (5)

Country Link
US (1) US5495487A (de)
EP (1) EP0358365B1 (de)
JP (1) JP2948835B2 (de)
KR (1) KR0165104B1 (de)
DE (1) DE68928837T2 (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6522985B1 (en) * 1989-07-31 2003-02-18 Texas Instruments Incorporated Emulation devices, systems and methods utilizing state machines
US6304987B1 (en) * 1995-06-07 2001-10-16 Texas Instruments Incorporated Integrated test circuit
EP0358376B1 (de) * 1988-09-07 1995-02-22 Texas Instruments Incorporated Integrierte Prüfschaltung
US5483518A (en) 1992-06-17 1996-01-09 Texas Instruments Incorporated Addressable shadow port and protocol for serial bus networks
EP0382360B1 (de) 1989-02-08 1997-03-19 Texas Instruments Incorporated Durch Ereigniss befähigte Prüfarchitektur für integrierte Schaltungen
JP3005250B2 (ja) * 1989-06-30 2000-01-31 テキサス インスツルメンツ インコーポレイテツド バスモニター集積回路
US6675333B1 (en) 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
US5550843A (en) * 1994-04-01 1996-08-27 Xilinx, Inc. Programmable scan chain testing structure and method
GB2288666B (en) * 1994-04-12 1997-06-25 Advanced Risc Mach Ltd Integrated circuit control
US5592681A (en) * 1994-06-14 1997-01-07 Texas Instruments Incorporated Data processing with improved register bit structure
JP2654352B2 (ja) * 1994-07-29 1997-09-17 日本電気アイシーマイコンシステム株式会社 半導体集積回路
JP2734394B2 (ja) * 1995-01-27 1998-03-30 日本電気株式会社 半導体集積回路装置
SE504041C2 (sv) * 1995-03-16 1996-10-21 Ericsson Telefon Ab L M Integrerat kretsarrangemang för provning
US5838934A (en) * 1995-06-07 1998-11-17 Texas Instruments Incorporated Host port interface
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US5648973A (en) * 1996-02-06 1997-07-15 Ast Research, Inc. I/O toggle test method using JTAG
JP3691170B2 (ja) * 1996-08-30 2005-08-31 株式会社ルネサステクノロジ テスト回路
US6028983A (en) * 1996-09-19 2000-02-22 International Business Machines Corporation Apparatus and methods for testing a microprocessor chip using dedicated scan strings
US6260165B1 (en) 1996-10-18 2001-07-10 Texas Instruments Incorporated Accelerating scan test by re-using response data as stimulus data
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6560734B1 (en) 1998-06-19 2003-05-06 Texas Instruments Incorporated IC with addressable test port
US6519729B1 (en) 1998-06-27 2003-02-11 Texas Instruments Incorporated Reduced power testing with equally divided scan paths
FR2783111B1 (fr) 1998-09-08 2000-10-13 St Microelectronics Sa Circuit integre comportant une cellule de test modifiee pour resynchroniser ledit circuit integre
US6397374B1 (en) * 1998-09-30 2002-05-28 National Semiconductor Corporation Zero hold time circuit for high speed bus applications
US6158034A (en) * 1998-12-03 2000-12-05 Atmel Corporation Boundary scan method for terminating or modifying integrated circuit operating modes
US7058862B2 (en) * 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
KR100337601B1 (ko) * 1999-09-27 2002-05-22 윤종용 내부 상태 모니터링 회로를 가지는 반도체 집적 회로 및 그를 이용한 내부 신호 모니터링 방법
DE60108993T2 (de) * 2000-03-09 2005-07-21 Texas Instruments Inc., Dallas Anpassung von "Scan-BIST"-Architekturen für einen Betrieb mit niedrigem Verbrauch
KR100377488B1 (ko) * 2000-07-20 2003-03-26 백우현 원적외선 황토타일 및 이의 제조방법
JP4228061B2 (ja) * 2000-12-07 2009-02-25 富士通マイクロエレクトロニクス株式会社 集積回路の試験装置および試験方法
KR100384419B1 (ko) * 2000-12-28 2003-05-22 우성세라믹스공업 주식회사 무정형 무늬 점토벽돌의 제조방법
US6904576B2 (en) * 2002-08-09 2005-06-07 Synplicity, Inc. Method and system for debugging using replicated logic
US7398445B2 (en) * 2002-08-09 2008-07-08 Synplicity, Inc. Method and system for debug and test using replicated logic
US7213216B2 (en) * 2002-08-09 2007-05-01 Synplicity, Inc. Method and system for debugging using replicated logic and trigger logic
KR100530831B1 (ko) * 2002-09-26 2005-11-23 우성세라믹스공업 주식회사 고령토(백토·점토), 장석 및 블랙그래눌을 활용한 도자기질 점토 벽돌 및 점토 바닥벽돌과 그 제조방법
US7682416B2 (en) 2004-02-17 2010-03-23 Donaldson Company, Inc. Air cleaner arrangements; serviceable filter elements; and, methods
JP2006329810A (ja) * 2005-05-26 2006-12-07 Nec Electronics Corp 半導体集積回路及びそのテスト方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4023142A (en) * 1975-04-14 1977-05-10 International Business Machines Corporation Common diagnostic bus for computer systems to enable testing concurrently with normal system operation
US4264807A (en) * 1979-04-09 1981-04-28 International Business Machines Corporation Counter including two 2 bit counter segments connected in cascade each counting in Gray code
JPS5618766A (en) * 1979-07-26 1981-02-21 Fujitsu Ltd Testing apparatus for logic circuit
DE3274910D1 (en) * 1982-09-28 1987-02-05 Ibm Device for loading and reading different chains of bistable circuits in a data processing system
US4513418A (en) * 1982-11-08 1985-04-23 International Business Machines Corporation Simultaneous self-testing system
DE3373729D1 (en) * 1983-12-08 1987-10-22 Ibm Deutschland Testing and diagnostic device for a digital calculator
DE3373730D1 (en) * 1983-12-15 1987-10-22 Ibm Series-parallel/parallel-series device for variable bit length configuration
US4602210A (en) * 1984-12-28 1986-07-22 General Electric Company Multiplexed-access scan testable integrated circuit
US4710933A (en) * 1985-10-23 1987-12-01 Texas Instruments Incorporated Parallel/serial scan system for testing logic circuits
US4710931A (en) * 1985-10-23 1987-12-01 Texas Instruments Incorporated Partitioned scan-testing system
US4701921A (en) * 1985-10-23 1987-10-20 Texas Instruments Incorporated Modularized scan path for serially tested logic circuit
US4698588A (en) * 1985-10-23 1987-10-06 Texas Instruments Incorporated Transparent shift register latch for isolating peripheral ports during scan testing of a logic circuit
JPH0746120B2 (ja) * 1986-03-10 1995-05-17 株式会社東芝 テスト容易化回路及びテスト方法
JPS6337270A (ja) * 1986-07-31 1988-02-17 Fujitsu Ltd 半導体装置
KR910002236B1 (ko) * 1986-08-04 1991-04-08 미쓰비시 뎅기 가부시끼가이샤 반도체집적회로장치
US4821269A (en) * 1986-10-23 1989-04-11 The Grass Valley Group, Inc. Diagnostic system for a digital signal processor
JPS63182585A (ja) * 1987-01-26 1988-07-27 Toshiba Corp テスト容易化機能を備えた論理回路
JPS63291134A (ja) * 1987-05-22 1988-11-29 Toshiba Corp 論理集積回路
US5084874A (en) * 1988-09-07 1992-01-28 Texas Instruments Incorporated Enhanced test circuit
US5056094A (en) * 1989-06-09 1991-10-08 Texas Instruments Incorporated Delay fault testing method and apparatus
US5056093A (en) * 1989-08-09 1991-10-08 Texas Instruments Incorporated System scan path architecture

Also Published As

Publication number Publication date
EP0358365A3 (de) 1991-06-12
KR0165104B1 (ko) 1999-04-15
EP0358365B1 (de) 1998-10-21
JP2948835B2 (ja) 1999-09-13
JPH02168176A (ja) 1990-06-28
EP0358365A2 (de) 1990-03-14
DE68928837D1 (de) 1998-11-26
KR900005472A (ko) 1990-04-14
US5495487A (en) 1996-02-27

Similar Documents

Publication Publication Date Title
DE68928837D1 (de) Prüf-Puffer/Register
KR890017426U (ko) 완충기
DE69032384D1 (de) Datenpuffer
DK315589D0 (da) Modul-indstikskort
DE68912277D1 (de) Ausgangspufferschaltung.
DE68928385T2 (de) Neuronenrechner
KR900701336A (ko) 역지 밸브
NO179739C (no) Kasse
BR8803391A (pt) Registrador
KR890700868A (ko) 금전등록기 카바
FI98565B (fi) Puskuritila
DE69030457D1 (de) Elastische Pufferspeicher
DE69027516D1 (de) Pufferschaltung
KR910000874U (ko) 문의 완충용 패킹
KR910005114U (ko) 출력버퍼
KR890016423U (ko) 창문용 완충구
KR900004589U (ko) 장기
KR910006612U (ko) 기구용 완충구조
KR890017809U (ko) 체크 밸브
KR890018651U (ko) 승차권 케이스
KR900005480U (ko) 간판용 프레임(frame)
FI882472A0 (fi) Till ventilationskakonstruktion
KR890021009U (ko) 완충용 포장재
KR900000121U (ko) 신발의 완충장치
BR6801752U (pt) Torcedor adaptavel

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee