DE69217524T2 - Testschaltung, vorgesehen in digitalen logischen Schaltungen - Google Patents

Testschaltung, vorgesehen in digitalen logischen Schaltungen

Info

Publication number
DE69217524T2
DE69217524T2 DE69217524T DE69217524T DE69217524T2 DE 69217524 T2 DE69217524 T2 DE 69217524T2 DE 69217524 T DE69217524 T DE 69217524T DE 69217524 T DE69217524 T DE 69217524T DE 69217524 T2 DE69217524 T2 DE 69217524T2
Authority
DE
Germany
Prior art keywords
test circuit
logic circuits
circuit provided
digital logic
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69217524T
Other languages
English (en)
Other versions
DE69217524D1 (de
Inventor
Hiroaki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69217524D1 publication Critical patent/DE69217524D1/de
Publication of DE69217524T2 publication Critical patent/DE69217524T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69217524T 1991-09-05 1992-09-04 Testschaltung, vorgesehen in digitalen logischen Schaltungen Expired - Fee Related DE69217524T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3225554A JP2770617B2 (ja) 1991-09-05 1991-09-05 テスト回路

Publications (2)

Publication Number Publication Date
DE69217524D1 DE69217524D1 (de) 1997-03-27
DE69217524T2 true DE69217524T2 (de) 1997-09-25

Family

ID=16831115

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69217524T Expired - Fee Related DE69217524T2 (de) 1991-09-05 1992-09-04 Testschaltung, vorgesehen in digitalen logischen Schaltungen

Country Status (4)

Country Link
US (1) US5392296A (de)
EP (1) EP0530835B1 (de)
JP (1) JP2770617B2 (de)
DE (1) DE69217524T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10120282A1 (de) * 2001-04-25 2002-11-07 Infineon Technologies Ag Bussignalhaltezelle, Bussystem und Verfahren

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5260950A (en) * 1991-09-17 1993-11-09 Ncr Corporation Boundary-scan input circuit for a reset pin
US6035262A (en) * 1994-06-27 2000-03-07 Tandem Computers Incorporated Real time observation serial scan test architecture
US5729553A (en) * 1994-08-29 1998-03-17 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit with a testable block
US5821773A (en) * 1995-09-06 1998-10-13 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
JP3691144B2 (ja) * 1995-12-20 2005-08-31 株式会社ルネサステクノロジ スキャンパス構成回路
US5869979A (en) * 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration
US5710779A (en) * 1996-04-09 1998-01-20 Texas Instruments Incorporated Real time data observation method and apparatus
US5748645A (en) * 1996-05-29 1998-05-05 Motorola, Inc. Clock scan design from sizzle global clock and method therefor
US6044481A (en) * 1997-05-09 2000-03-28 Artisan Components, Inc. Programmable universal test interface for testing memories with different test methodologies
US5968192A (en) * 1997-05-09 1999-10-19 Artisan Components, Inc. Programmable universal test interface and method for making the same
US6125464A (en) * 1997-10-16 2000-09-26 Adaptec, Inc. High speed boundary scan design
JP3145976B2 (ja) * 1998-01-05 2001-03-12 日本電気アイシーマイコンシステム株式会社 半導体集積回路
JP3092704B2 (ja) 1998-02-17 2000-09-25 日本電気株式会社 大規模集積回路およびそのボードテスト方法
US6184707B1 (en) 1998-10-07 2001-02-06 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
EP1286170A1 (de) * 2001-08-14 2003-02-26 Lucent Technologies Inc. Flipflop für "Boundary-Scan" mit Bypass für die Speicherzelle des Flipflops
US7404128B2 (en) 2004-02-17 2008-07-22 Texas Instruments Incorporated Serial data I/O on JTAG TCK with TMS clocking
KR100728358B1 (ko) * 2004-02-19 2007-06-13 엘지전자 주식회사 방열장치
US7649379B2 (en) * 2007-12-26 2010-01-19 Texas Instruments Incorporated Reducing mission signal output delay in IC having mission and test modes
WO2009084424A1 (ja) 2007-12-28 2009-07-09 Nec Corporation 半導体テスト装置、半導体装置および試験方法
US8073996B2 (en) * 2008-01-09 2011-12-06 Synopsys, Inc. Programmable modular circuit for testing and controlling a system-on-a-chip integrated circuit, and applications thereof

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2902375C2 (de) * 1979-01-23 1984-05-17 Siemens AG, 1000 Berlin und 8000 München Logikbaustein für integrierte Digitalschaltungen
JPS60223250A (ja) * 1984-04-19 1985-11-07 Toshiba Corp 情報伝送装置
US4710927A (en) * 1986-07-24 1987-12-01 Integrated Device Technology, Inc. Diagnostic circuit
KR900002770B1 (ko) * 1986-08-04 1990-04-30 미쓰비시 뎅끼 가부시끼가이샤 반도체 집적회로장치
KR910002236B1 (ko) * 1986-08-04 1991-04-08 미쓰비시 뎅기 가부시끼가이샤 반도체집적회로장치
JP2628154B2 (ja) * 1986-12-17 1997-07-09 富士通株式会社 半導体集積回路
US4833676A (en) * 1987-07-30 1989-05-23 Hughes Aircraft Company Interleaved method and circuitry for testing for stuck open faults
JPH0769396B2 (ja) * 1988-04-01 1995-07-31 日本電気株式会社 半導体集積回路装置
JPH03252569A (ja) * 1990-02-26 1991-11-11 Advanced Micro Devicds Inc スキャンパス用レジスタ回路
JP2513904B2 (ja) * 1990-06-12 1996-07-10 株式会社東芝 テスト容易化回路
EP0462328A1 (de) * 1990-06-18 1991-12-27 ALCATEL BELL Naamloze Vennootschap Testanordnung für einen elektronischen Chip
US5130988A (en) * 1990-09-17 1992-07-14 Northern Telecom Limited Software verification by fault insertion
US5291495A (en) * 1991-07-12 1994-03-01 Ncr Corporation Method for designing a scan path for a logic circuit and testing of the same
US5260950A (en) * 1991-09-17 1993-11-09 Ncr Corporation Boundary-scan input circuit for a reset pin

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10120282A1 (de) * 2001-04-25 2002-11-07 Infineon Technologies Ag Bussignalhaltezelle, Bussystem und Verfahren
DE10120282B4 (de) * 2001-04-25 2005-08-18 Infineon Technologies Ag Bussignalhaltezelle und Verfahren

Also Published As

Publication number Publication date
JP2770617B2 (ja) 1998-07-02
EP0530835A1 (de) 1993-03-10
JPH0560835A (ja) 1993-03-12
EP0530835B1 (de) 1997-02-19
US5392296A (en) 1995-02-21
DE69217524D1 (de) 1997-03-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee