KR880013247A - 반도체 장치의 제조방법 - Google Patents

반도체 장치의 제조방법 Download PDF

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Publication number
KR880013247A
KR880013247A KR870004242A KR870004242A KR880013247A KR 880013247 A KR880013247 A KR 880013247A KR 870004242 A KR870004242 A KR 870004242A KR 870004242 A KR870004242 A KR 870004242A KR 880013247 A KR880013247 A KR 880013247A
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KR
South Korea
Prior art keywords
trench
polysilicon
forming
manufacturing
semiconductor device
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Application number
KR870004242A
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English (en)
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KR900003262B1 (ko
Inventor
송주호
한대희
강긍원
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019870004242A priority Critical patent/KR900003262B1/ko
Priority to GB08808824A priority patent/GB2205993A/en
Priority to FR888805041A priority patent/FR2614731B1/fr
Priority to JP63091865A priority patent/JPS63299263A/ja
Priority to DE3812621A priority patent/DE3812621A1/de
Priority to NL8801030A priority patent/NL8801030A/nl
Publication of KR880013247A publication Critical patent/KR880013247A/ko
Application granted granted Critical
Publication of KR900003262B1 publication Critical patent/KR900003262B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 이상적으로 트렌치가 형성된 트렌치 캐패시터, 제2(A)-(B)도는 언더컬현상이 발생한 트렌치로 형성한 종래의 트렌치 캐패시터, 제3(A)-(E)도는 본 발명의 트렌치 캐패시터 제조공정도.

Claims (3)

  1. 트렌치 캐패시터의 제조방법에 있어서, 실리콘 반도체기판(10)상에 산화막(11)을 형성하고 이방성에칭으로 트렌치(12)를 형성하는 제 1 공정과, 상기 제 1 공정의 트렌치(12)의 측변에 캐패시터절연막(13)을 형성하고 소정두께의 폴리실리콘(14)을 형성하는 제 2 공정과, 상기 제 2 공정의 폴리실리콘(14)을 에치백하여 상기 제 1 공정의 트렌치(12)벽면 언더컬현상과 무관한 트렌치(16)를 형상하는 제 3 공정과, 상기 제 3 공정에서 형성된 트렌치(16)에 폴리실리콘(17)을 채우는 제 4 공정과, 상기 제 4 공정의 폴리실리콘(17)을 에치백하여 실리콘기판을 평탄화한 후 폴리실리콘전극(18)을 형성하는 제 5 공정으로 이루어짐을 특징으로 하는 반도체 장치의 제조방법.
  2. 상기 제 1 항의 제 1 공정에 있어서, 트렌치의 에칭조건이 BCI3은 5-25SCCM, CI2는 30-55SCCM, 압력은 10-30miorr, 전압은 직류로 -200------300V가 됨을 특징으로 하는 반도체 장치의 제조방법.
  3. 상기 제 1 항의 제 2 공정에 있어서, 폴리실리콘의 두께는 상기 제 1 공정에서 형성된 트렌치 개구부폭의 0.3-0.4배가 됨을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870004242A 1987-04-30 1987-04-30 반도체 장치의 제조방법 KR900003262B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019870004242A KR900003262B1 (ko) 1987-04-30 1987-04-30 반도체 장치의 제조방법
GB08808824A GB2205993A (en) 1987-04-30 1988-04-14 Method of manufacturing a trench capacitor
FR888805041A FR2614731B1 (fr) 1987-04-30 1988-04-15 Procede de fabrication d'un condensateur en tranchee pour circuit integre
JP63091865A JPS63299263A (ja) 1987-04-30 1988-04-15 半導体装置の製造方法
DE3812621A DE3812621A1 (de) 1987-04-30 1988-04-15 Verfahren zum herstellen eines grabenkondensators, beispielsweise fuer speicherzellen
NL8801030A NL8801030A (nl) 1987-04-30 1988-04-21 Productiemethode voor een groefcondensator.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870004242A KR900003262B1 (ko) 1987-04-30 1987-04-30 반도체 장치의 제조방법

Publications (2)

Publication Number Publication Date
KR880013247A true KR880013247A (ko) 1988-11-30
KR900003262B1 KR900003262B1 (ko) 1990-05-12

Family

ID=19261098

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870004242A KR900003262B1 (ko) 1987-04-30 1987-04-30 반도체 장치의 제조방법

Country Status (6)

Country Link
JP (1) JPS63299263A (ko)
KR (1) KR900003262B1 (ko)
DE (1) DE3812621A1 (ko)
FR (1) FR2614731B1 (ko)
GB (1) GB2205993A (ko)
NL (1) NL8801030A (ko)

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5681968A (en) * 1979-12-07 1981-07-04 Toshiba Corp Manufacture of semiconductor device
DE3045922A1 (de) * 1980-12-05 1982-07-08 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von strukturen von aus siliziden oder aus silizid-polysilizium bestehenden schichten durch reaktives sputteraetzen
US4450042A (en) * 1982-07-06 1984-05-22 Texas Instruments Incorporated Plasma etch chemistry for anisotropic etching of silicon
DE3315719A1 (de) * 1983-04-29 1984-10-31 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von strukturen von aus metallsiliziden bzw. silizid-polysilizium bestehenden doppelschichten fuer integrierte halbleiterschaltungen durch reaktives ionenaetzen
JPS6079737A (ja) * 1983-10-05 1985-05-07 Nec Corp 半導体装置の製造方法
JPS60126861A (ja) * 1983-12-13 1985-07-06 Fujitsu Ltd 半導体記憶装置
JPS61288460A (ja) * 1985-06-17 1986-12-18 Nippon Telegr & Teleph Corp <Ntt> 半導体記憶装置およびその製造方法
US4714520A (en) * 1985-07-25 1987-12-22 Advanced Micro Devices, Inc. Method for filling a trench in an integrated circuit structure without producing voids
US4801988A (en) * 1986-10-31 1989-01-31 International Business Machines Corporation Semiconductor trench capacitor cell with merged isolation and node trench construction

Also Published As

Publication number Publication date
JPH0520908B2 (ko) 1993-03-22
NL8801030A (nl) 1988-11-16
FR2614731A1 (fr) 1988-11-04
GB2205993A (en) 1988-12-21
GB8808824D0 (en) 1988-05-18
DE3812621A1 (de) 1988-11-17
KR900003262B1 (ko) 1990-05-12
JPS63299263A (ja) 1988-12-06
FR2614731B1 (fr) 1992-01-03

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