JPS6481357A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6481357A
JPS6481357A JP62237248A JP23724887A JPS6481357A JP S6481357 A JPS6481357 A JP S6481357A JP 62237248 A JP62237248 A JP 62237248A JP 23724887 A JP23724887 A JP 23724887A JP S6481357 A JPS6481357 A JP S6481357A
Authority
JP
Japan
Prior art keywords
film
sidewall
gate
sio2
remains
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62237248A
Other languages
Japanese (ja)
Inventor
Kentaro Yoshioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62237248A priority Critical patent/JPS6481357A/en
Publication of JPS6481357A publication Critical patent/JPS6481357A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To prevent a breakdown strength and wiring resistance from decreasing due to the use of an Si3N4 film cell gate by forming the sidewall film of a thick insulating film on the sidewall of a memory cell gate. CONSTITUTION:An isolating thick field SiO2 film 52 is formed in an Si substrate 51, a gate SiO2 film 55, a gate Si3N4 film 54, and a first gate polysilicon film 53 are sequentially formed, and a capacitor 56 is formed by photolithographic etching. Then, an SiO2 film or a PSG film 57 is deposited as an insulating film by a normal pressure CVD method on a whole surface. In this case, the film thickness t1 on the film 52 becomes larger than that t2 on the substrate 51. When the film 57 is so etched as to remove only the film thickness of the t2, an insulating film 62 remains on the film 52, and a sidewall film 63 thicker than the film 53 remains on the sidewall of the film 53. The breakdown strength characteristics of a transfer electrode 68 to be formed in later step and the film 53 are improved due to the remainder of the film 63.
JP62237248A 1987-09-24 1987-09-24 Manufacture of semiconductor device Pending JPS6481357A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62237248A JPS6481357A (en) 1987-09-24 1987-09-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62237248A JPS6481357A (en) 1987-09-24 1987-09-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6481357A true JPS6481357A (en) 1989-03-27

Family

ID=17012595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62237248A Pending JPS6481357A (en) 1987-09-24 1987-09-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6481357A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105914138A (en) * 2016-06-24 2016-08-31 上海华虹宏力半导体制造有限公司 PIP (Poly-Insulator-Poly) capacitor process method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105914138A (en) * 2016-06-24 2016-08-31 上海华虹宏力半导体制造有限公司 PIP (Poly-Insulator-Poly) capacitor process method

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