JPS6430259A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6430259A
JPS6430259A JP62186399A JP18639987A JPS6430259A JP S6430259 A JPS6430259 A JP S6430259A JP 62186399 A JP62186399 A JP 62186399A JP 18639987 A JP18639987 A JP 18639987A JP S6430259 A JPS6430259 A JP S6430259A
Authority
JP
Japan
Prior art keywords
insulating film
silicon
layer
trench
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62186399A
Other languages
Japanese (ja)
Inventor
Hiroshi Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62186399A priority Critical patent/JPS6430259A/en
Publication of JPS6430259A publication Critical patent/JPS6430259A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To enable the use of a (1/2) Vcc method and make a capacitor insulating film thinner and larger enough in capacitance by a method wherein an insulating film is provided between a supporting substrate and an element substrate. CONSTITUTION:An insulating layer 11 of silicon oxide or silicon nitride is formed on a supporting substrate 10 of a P-type silicon, a semiconductor layer (element substrate) 12 is deposited thereon, a field oxide film 13 is provided, and a trench 14a is formed through the usual trench etching. A capacitor insulating film 14b of silicon oxide is formed on an inner wall of the trench 14 and the surface of the semiconductor layer 12 through the thermal oxidation, polycrystalline is embedded for the formation of a polycrystalline silicon layer 14c. Next, the insulating film 14b is removed, the polycrystalline silicon layer 14c is newly embedded, a silicon oxide film (gate oxide film) is provided, and a charge storage storage section 14 is formed.
JP62186399A 1987-07-24 1987-07-24 Semiconductor device Pending JPS6430259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62186399A JPS6430259A (en) 1987-07-24 1987-07-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62186399A JPS6430259A (en) 1987-07-24 1987-07-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6430259A true JPS6430259A (en) 1989-02-01

Family

ID=16187721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62186399A Pending JPS6430259A (en) 1987-07-24 1987-07-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6430259A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0703625A3 (en) * 1994-09-26 1999-03-03 Siemens Aktiengesellschaft Deep trench DRAM process on SOI for low leakage DRAM cell
CN100345305C (en) * 1992-01-09 2007-10-24 国际商业机器公司 Double-gate substrate danamic RAM cell array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100345305C (en) * 1992-01-09 2007-10-24 国际商业机器公司 Double-gate substrate danamic RAM cell array
EP0703625A3 (en) * 1994-09-26 1999-03-03 Siemens Aktiengesellschaft Deep trench DRAM process on SOI for low leakage DRAM cell

Similar Documents

Publication Publication Date Title
KR940001352A (en) Trench device isolation method
JPS64756A (en) Semiconductor device and capacitor device and manufacture thereof
KR960008518B1 (en) Manufacturing method and apparatus of semiconductor device
JPS55163860A (en) Manufacture of semiconductor device
JPS6427252A (en) Semiconductor storage device
JPS6467945A (en) Wiring layer formed on buried dielectric and manufacture thereof
WO2001095391A8 (en) Self-limiting polysilicon buffered locos for dram trench capacitor collar
US5369052A (en) Method of forming dual field oxide isolation
EP0029552A3 (en) Method for producing a semiconductor device
TW363216B (en) Manufacturing method of capacitor used for DRAM
JPS6430259A (en) Semiconductor device
JPS6472551A (en) Manufacture of trench capacitor
JPS57191539A (en) Semiconductor ion sensor
EP0278159A3 (en) Method of manufacturing a semiconductor device comprising an isolation structure
JPS57204146A (en) Manufacture of semiconductor device
JPS6457641A (en) Manufacture of semiconductor device
JPS6481368A (en) Nonvolatile semiconductor device
JPS5763842A (en) Preparation of semiconductor integrated circuit
JPS6428962A (en) Semiconductor device and manufacture thereof
JPS6425555A (en) Trench forming method
JPS54153583A (en) Semiconductor device
KR940012574A (en) Method of forming insulating film for device isolation
EP0067738A3 (en) Method of reducing encroachment in a semiconductor device
KR890004415A (en) Device Separation Method of Semiconductor Device
KR920001733B1 (en) Manufacturing method of highly integrated dram cell