KR890004415A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR890004415A
KR890004415A KR1019870008770A KR870008770A KR890004415A KR 890004415 A KR890004415 A KR 890004415A KR 1019870008770 A KR1019870008770 A KR 1019870008770A KR 870008770 A KR870008770 A KR 870008770A KR 890004415 A KR890004415 A KR 890004415A
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South Korea
Prior art keywords
oxide film
layer
film layer
etching
substrate
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KR1019870008770A
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Korean (ko)
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KR900001059B1 (en
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류현기
김병렬
박문진
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강진구
상성반도체통신 주식회사
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Priority to KR1019870008770A priority Critical patent/KR900001059B1/en
Publication of KR890004415A publication Critical patent/KR890004415A/en
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Publication of KR900001059B1 publication Critical patent/KR900001059B1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

Abstract

요약 없음No summary

Description

반도체장치의 소자 분리방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2 (A)-(J),(A)-(D)-(E')-(J')도는 본 발명에 따른 제조공정도, 제3도는 트렌치 캐패시터 제조에 사용될 소잡분리영역 단면도.2 (A)-(J), (A)-(D)-(E ')-(J') are sectional views of the manufacturing process according to the present invention, and FIG.

Claims (3)

반도체장치의 제조방법에 있어서, 실리콘 반도체기판(10)상에 제1산화막층In the method of manufacturing a semiconductor device, a first oxide film layer on a silicon semiconductor substrate 10 (11), 제1질화막층(12), 폴리실리콘층(13)을 순차적으로 형성하고 포트레지스트(11), the first nitride film layer 12 and the polysilicon layer 13 are sequentially formed, and the photoresist (14)을 형성한후 폴리실콘층(13)을 에칭하여 창(15a)을 형성하는 제1공정과, 상기 포트레지스트(14)를 제거하고 폴리실콘층(13)을 산화시켜 제2산화막층(16)을 형성하는 제2공정과, 상기 제2산화막층(16)을 마스크로하여 제1질화막층(12), 제1산화막층(11)과 소정길이의 기판(10)을 에칭하여 제1트렌치(17)를 형성하는 제3공정과, 상기 제1트렌치(17)내부에 얇은 제3산화막(18)을 성장시키는 제4공정과, 반도체 기판 전면에 제2질화막(19)을 침적시키고 에치백하는 제5공정과, 별도의 마스크 없이 반도체기판을 에칭하여 제2트렌치(20)를 형성하는 제6공정과, 상기 제2산화막Forming the window 15a by etching the polysilicon layer 13 after forming the layer 14, and removing the photoresist 14 and oxidizing the polysilicon layer 13 to oxidize the second oxide film layer. (2) forming the first nitride film layer 12, the first oxide film layer 11 and the substrate 10 having a predetermined length by etching the second oxide film layer 16 as a mask. A third process of forming one trench 17, a fourth process of growing a thin third oxide film 18 inside the first trench 17, and depositing a second nitride film 19 on the entire surface of the semiconductor substrate. A fifth process of etching back, a sixth process of etching the semiconductor substrate without a mask to form a second trench 20, and the second oxide film (16)을 에칭하는 제7공정과, 산화공정으로 상기 제2트렌치(20) 내부에 제4산화막층A fourth oxide film layer inside the second trench 20 by a seventh step of etching the 16 and an oxidation step (21)을 형성하는 제8공정과, 기판 상부의 모든 질화막(12)(19)을 제거하는 제9공정과, 기판상부의 제1산화막층(11)을 제거하는 제10공정으로 이루어짐을 특징으로 하는 반도체장치 소자 분리방법.An eighth step of forming 21, a ninth step of removing all the nitride films 12, 19 on the substrate, and a tenth step of removing the first oxide layer 11 on the substrate. A semiconductor device element separation method. 반도체장치의 제조방법에 있어서, 실리콘 반도체기판(10)상에 제1산화막층In the method of manufacturing a semiconductor device, a first oxide film layer on a silicon semiconductor substrate 10 (11), 제1질화막층(12), 폴리실리콘층(13)을 순차적으로 형성하고 포트레지스트 패턴(14)를 형성한후 폴리실콘층(13)을 에칭하여 창(15a)을 형성하는 제1공정과, 상기 포트레지스트(14)를 제거하고 폴리실콘층(13)을 산화시켜 제2산화막층(16)을 형성하는 제2공정과, 상기 제2산화막층(16)을 마스크로하여 제1질화막층(12), 제1산화막층(11)과 소정깊이의 기판(10)을 에칭하여 제1트렌치를 형성하는 제3공정과, 상기 제1트렌치 내부에 얇은 제3산화막(18)을 성장시키는 제4공정과, 반도체기판 전면에 폴리실콘(22)을 침적시키고 별도의 마스크 없이 반도체기판을 에칭하여 제2트렌치(23)를 형성하는 제5공정과, 상기 제2산화막(16)을 에칭한 제6공정과, 산화공정으로 상기 제2트렌치(23) 내부에 제4산화막층(24)을 형성하는 제7공정과, 기판상부의 제1질화막(12)을 제거하는 제8공정과, 기판상부의 제1산화막층(11)을 제거하는 제9공정으로 이루어짐을 특징으로 하는 반도체장치의 소자 분리방법.(11), the first nitride film layer 12 and the polysilicon layer 13 are sequentially formed, and the photoresist pattern 14 is formed, and then the polysilicon layer 13 is etched to form the window 15a. A second step of forming the second oxide film layer 16 by removing the pot resist 14 and oxidizing the polysilicon layer 13, and using the second oxide film layer 16 as a mask. A third process of etching the first nitride film layer 12, the first oxide film layer 11 and the substrate 10 having a predetermined depth to form a first trench, and a thin third oxide film 18 inside the first trench. A fourth step of growing the second substrate; and a fifth step of forming the second trenches 23 by depositing the polysilicon 22 on the entire surface of the semiconductor substrate and etching the semiconductor substrate without a separate mask, and the second oxide film 16. A sixth step of etching, a seventh step of forming a fourth oxide film layer 24 inside the second trench 23 by an oxidation process, and an eighth hole of removing the first nitride film 12 on the substrate And a device isolation method for a semiconductor device, characterized by constituted by any ninth step of removing the first oxide layer 11 of the upper substrate. 제2항에 있어서, 제1공정에서 제5공정, 제7공정의 연속공정에 의해 소자 분리영역을 형성하고 상기 소자 분리영역 제조공정중에 반도체 기판상에 형성된 산화막층을 트렌치 에칭공정시 마스크층으로 사용함을 특징으로 하는 반도체장치의 소자 분리방법.The method of claim 2, wherein the device isolation region is formed by a continuous process of the first to fifth processes, and the oxide layer formed on the semiconductor substrate during the manufacturing process of the device isolation region as a mask layer during the trench etching process. Device separation method of a semiconductor device, characterized in that the use. ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870008770A 1987-08-11 1987-08-11 Isolation method of semiconductor device KR900001059B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870008770A KR900001059B1 (en) 1987-08-11 1987-08-11 Isolation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870008770A KR900001059B1 (en) 1987-08-11 1987-08-11 Isolation method of semiconductor device

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KR890004415A true KR890004415A (en) 1989-04-21
KR900001059B1 KR900001059B1 (en) 1990-02-26

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990065818A (en) * 1998-01-16 1999-08-05 구자홍 Health check device linked to wireless network
KR100336543B1 (en) * 1993-09-23 2002-11-29 코닌클리케 필립스 일렉트로닉스 엔.브이. Semiconductor device manufacturing method
KR100849079B1 (en) * 2002-06-28 2008-07-30 매그나칩 반도체 유한회사 Method for element isolating of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100336543B1 (en) * 1993-09-23 2002-11-29 코닌클리케 필립스 일렉트로닉스 엔.브이. Semiconductor device manufacturing method
KR19990065818A (en) * 1998-01-16 1999-08-05 구자홍 Health check device linked to wireless network
KR100849079B1 (en) * 2002-06-28 2008-07-30 매그나칩 반도체 유한회사 Method for element isolating of semiconductor device

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Publication number Publication date
KR900001059B1 (en) 1990-02-26

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