JPS61201444A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61201444A
JPS61201444A JP60042351A JP4235185A JPS61201444A JP S61201444 A JPS61201444 A JP S61201444A JP 60042351 A JP60042351 A JP 60042351A JP 4235185 A JP4235185 A JP 4235185A JP S61201444 A JPS61201444 A JP S61201444A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
substrate
oxide film
silicon oxide
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60042351A
Other languages
Japanese (ja)
Inventor
Satoyuki Ando
安藤 智行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60042351A priority Critical patent/JPS61201444A/en
Publication of JPS61201444A publication Critical patent/JPS61201444A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

Abstract

PURPOSE:To improve a rate of integration of a CMOS integrated circuit without causing a latch-up phenomenon by separating elements securely. CONSTITUTION:A silicon oxide film 2 as a buffer is formed by oxidizing a surface of a silicon substrate 1 and an SiN film 3 is formed on it. After the surface of the SiN film 3 is patterned by a photoresist 4 or the like, grooves 5 are formed in the substrate 1 by isotropic etching. A silicon oxide film 6 as a buffer is formed by oxidizing the inside surface of the groove 5. After a thin SiN film 7 is formed on the substrate, grooves 8 are further formed in the substrate 1 by etching the bottoms of the grooves 5. By oxidizing the exposed substrate 1, an oxide domain 9 is formed to separate an element forming domain 1'. The SiN films 3 and 7 are removed and the grooves 8 are filled with oxide films 10. With this constitution, the element forming domain 1' is completely separated from the substrate 1 by the oxide domain 9.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は(1108(相補型MO8)集積回路に適した
半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device suitable for a (1108 (complementary MO8) integrated circuit).

〔発凹の技術的背景とその問題点〕[Technical background of denting and its problems]

従来のCMO8集積回路では、素子を微細化し集積度を
上げていくと、外部雑音等によりいわゆるラッチアップ
現象を起こしゃすくなり。
In conventional CMO8 integrated circuits, as elements are made smaller and the degree of integration is increased, so-called latch-up phenomena are more likely to occur due to external noise, etc.

そのため集積度の増加に困難をきたしている。This makes it difficult to increase the degree of integration.

上記ラッチアップ現象を防止しかつ集積度を向上させる
には、現在法の2つの技術が考えられている。(イ)8
0 I (5ilicon On In5ulator
)つまり絶縁体上に素子部を各々分離して作成する方法
、 (01素子分離を、素子間に溝を堀って絶縁物を埋
め込むことにより行なう方法。
Two techniques are currently being considered to prevent the latch-up phenomenon and improve the degree of integration. (a) 8
0 I (5ilicon On In5ulator
) That is, a method in which the element parts are separated from each other on an insulator, and (01) a method in which element isolation is performed by digging trenches between elements and filling them with an insulator.

しかしながら上記(イ)の方法では、基板としての絶縁
物上に、シリコンをエピタキシャルに作成するのが難し
く、チップ価格も高価になる。
However, in the method (a) above, it is difficult to epitaxially form silicon on an insulator as a substrate, and the chip price becomes high.

上記(ロ)の方法では、素子の分離が完全に行なわれな
いものであった。
In the method (b) above, elements cannot be completely separated.

〔発明の目的〕[Purpose of the invention]

本発明は上記実情に鑑みてなされたもので。 The present invention has been made in view of the above circumstances.

前記従来技術の後者の方法を進めて素子間分離を完全に
行ない、CMO8集積回路の集積度を向上することがで
きる半導体装置の製造方法を提供しようとするものであ
る、 〔発すの概要〕 本発明は、半導体基板表面にシリコン酸化膜を形成しそ
の上にシリコン窒化膜を形成後、素子分離領域の前記シ
リコン窒化膜、シリコン酸化膜をエツチングしかつ適当
な深さまで前記半導体基板をエツチングした溝を形成す
る工程と。
This paper aims to provide a method for manufacturing a semiconductor device that can improve the degree of integration of a CMO8 integrated circuit by advancing the latter method of the prior art to completely isolate elements and improve the degree of integration of a CMO8 integrated circuit. In the present invention, a silicon oxide film is formed on the surface of a semiconductor substrate, a silicon nitride film is formed thereon, and then the silicon nitride film and silicon oxide film in an element isolation region are etched, and the semiconductor substrate is etched to an appropriate depth. and the process of forming.

この工程で露出した半導体基板表面にシリコン酸化膜を
形成しその上にシリコン窒化膜を形成後、前記半導体基
板に形成した溝の底のシリコン窒化膜、シリコン酸化膜
を除去しかつ適当な深さまで半導体基板をエツチングす
る工程と。
After forming a silicon oxide film on the surface of the semiconductor substrate exposed in this process and forming a silicon nitride film on it, the silicon nitride film and silicon oxide film at the bottom of the trench formed in the semiconductor substrate are removed and the silicon oxide film is removed to an appropriate depth. A process of etching a semiconductor substrate.

この工程で露出した半導体基板を酸化し該半導体基板の
素子形成領域の下部に酸化領域を形成でる工程とを具備
したものである。
This method includes a step of oxidizing the semiconductor substrate exposed in this step to form an oxidized region under the element formation region of the semiconductor substrate.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照して本発明の一実施例を説聞する。まず
第1図(alに示される如く、シリコン基板1の表面を
酸化して緩衝材としてのシリコン酸化膜2を形成し、そ
の上にSiN膜3をデポジションにより形成する。次に
第1図(b)に示される如く、ホトレジスト4等を用い
て素子分離領域のパターニングを行ない、その後RIE
(Reactive Ion Etching )%の
等方性エツチングで、基板1に溝5を形成する。その後
第1図(C)に示される如く、溝内部の酸化を行なうこ
とにより、緩衝材としてのシリコン酸化膜6を形成する
。この酸化膜6は前記酸化膜2と同程度の酸化により形
成したものである。次にIJI図(d)に示される如く
、基板上にSiN膜2をデポジションにより形成する。
An embodiment of the present invention will be explained below with reference to the drawings. First, as shown in FIG. 1 (al), the surface of a silicon substrate 1 is oxidized to form a silicon oxide film 2 as a buffer material, and a SiN film 3 is formed thereon by deposition.Next, as shown in FIG. As shown in (b), element isolation regions are patterned using photoresist 4, etc., and then RIE
(Reactive Ion Etching) Grooves 5 are formed in the substrate 1 by isotropic etching. Thereafter, as shown in FIG. 1C, the inside of the trench is oxidized to form a silicon oxide film 6 as a buffer material. This oxide film 6 is formed by oxidation to the same degree as the oxide film 2. Next, as shown in IJI diagram (d), a SiN film 2 is formed on the substrate by deposition.

この8iN膜2は8iN膜3よりかなり薄く形成する。This 8iN film 2 is formed much thinner than the 8iN film 3.

次に第1図(elに示される如<、RIE等により溝5
の底部をエツチングし、基板1に更に溝8を形成する。
Next, as shown in FIG. 1 (el), the groove 5 is
Further grooves 8 are formed in the substrate 1 by etching the bottom of the substrate 1.

次に第1図(flに示される如く、溝8の形成により露
出された基板1の酸化を行ない。
Next, as shown in FIG. 1 (fl), the substrate 1 exposed by the formation of the groove 8 is oxidized.

酸化領域9を形成して素子形成領域1′を分離する。次
に第1図(鎖に示す如(SiN膜3,7を除去し、酸化
膜10の埋め込みをする。この工程の一例としては、全
面にCVD法で酸化膜のデポジションを行ない、更にそ
の上にレジストを塗布し、その後このレジスト及び酸化
膜をエツチングすればよい。
Oxidized regions 9 are formed to isolate element forming regions 1'. Next, as shown in FIG. A resist may be applied thereon, and then the resist and oxide film may be etched.

このようにして形成された素子形成領域1′は、酸化領
域9で基板1から完全に分離され。
The element forming region 1' thus formed is completely separated from the substrate 1 by the oxidized region 9.

集積度を上げた際のラッテアップを確実に防止できるも
のである。
This can reliably prevent latte-up when the degree of integration is increased.

なお本発明は上記実施例のみに限らず、種々の応甲が可
能である。例えば第1図(glでは、隣°接酸化領域9
どうしが素子形成領域1′下で交わるまで酸化を行なっ
たが、交わる前に酸化をとめても、かなりのラッチアッ
プ防止効果を期待できる。
Note that the present invention is not limited to the above-mentioned embodiments, and various modifications are possible. For example, in FIG.
Although oxidation was performed until they intersected under the element formation region 1', a considerable latch-up prevention effect can be expected even if the oxidation is stopped before they intersect.

〔発明の効果〕〔Effect of the invention〕

以上説−した如く本発明によれば、素子分離が確実に行
なえ、ラッチアップ現象を生じることなく:CMO8集
積回路の集積度の向上が図れるものである。
As described above, according to the present invention, element isolation can be performed reliably and the degree of integration of a CMO8 integrated circuit can be improved without causing latch-up phenomena.

【図面の簡単な説明】 第1図(a)ないしくg)は本発明の一実施例を示す製
造工程図である。 1・・・半導体基板、2,6・・・シリコン酸化膜。 3.7・・・8iNII!、4・・・レジスト、5,8
・・・溝。
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1(a) to 1(g) are manufacturing process diagrams showing one embodiment of the present invention. 1... Semiconductor substrate, 2, 6... Silicon oxide film. 3.7...8iNII! , 4... resist, 5, 8
···groove.

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板表面にシリコン酸化膜を形成しその上
にシリコン窒化膜を形成後、素子分離領域の前記シリコ
ン窒化膜、シリコン酸化膜をエッチングしかつ適当な深
さまで前記半導体基板をエッチングした溝を形成する第
1の工程と、この工程で露出した半導体基板表面にシリ
コン酸化膜を形成しその上にシリコン窒化膜を形成後、
前記半導体基板に形成した溝の底のシリコン窒化膜、シ
リコン酸化膜を除去しかつ適当な深さまで半導体基板を
エッチングする第2の工程と、この工程で露出した半導
体基板を酸化し該半導体基板の素子形成領域の下部に酸
化領域を形成する第3の工程とを具備したことを特徴と
する半導体装置の製造方法。
(1) After forming a silicon oxide film on the surface of a semiconductor substrate and forming a silicon nitride film thereon, the silicon nitride film and the silicon oxide film in the element isolation region are etched, and the groove is etched in the semiconductor substrate to an appropriate depth. After forming a silicon oxide film on the surface of the semiconductor substrate exposed in this step and forming a silicon nitride film on it,
A second step of removing the silicon nitride film and silicon oxide film at the bottom of the groove formed in the semiconductor substrate and etching the semiconductor substrate to an appropriate depth, and oxidizing the semiconductor substrate exposed in this step to remove the silicon oxide film from the bottom of the groove formed in the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: a third step of forming an oxidized region below the element forming region.
(2)前記第2の工程で行なう半導体基板のエッチング
は、リアクティブ・イオン・エッチングであることを特
徴とする特許請求の範囲第1項に記載の半導体装置の製
造方法。
(2) The method of manufacturing a semiconductor device according to claim 1, wherein the etching of the semiconductor substrate performed in the second step is reactive ion etching.
(3)前記第3の工程において、前記酸化領域どうしが
前記半導体基板の素子形成領域下で交わるまで前記半導
体基板を酸化することを特徴とする特許請求の範囲第1
項に記載の半導体装置の製造方法。
(3) In the third step, the semiconductor substrate is oxidized until the oxidized regions intersect under the element formation region of the semiconductor substrate.
A method for manufacturing a semiconductor device according to paragraph 1.
JP60042351A 1985-03-04 1985-03-04 Manufacture of semiconductor device Pending JPS61201444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60042351A JPS61201444A (en) 1985-03-04 1985-03-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60042351A JPS61201444A (en) 1985-03-04 1985-03-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61201444A true JPS61201444A (en) 1986-09-06

Family

ID=12633609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60042351A Pending JPS61201444A (en) 1985-03-04 1985-03-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61201444A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63271952A (en) * 1987-04-28 1988-11-09 Nec Corp Manufacture of semiconductor device
US5112771A (en) * 1987-03-20 1992-05-12 Mitsubishi Denki Kabushiki Kaisha Method of fibricating a semiconductor device having a trench
US6110798A (en) * 1996-01-05 2000-08-29 Micron Technology, Inc. Method of fabricating an isolation structure on a semiconductor substrate
US6465865B1 (en) 1996-01-05 2002-10-15 Micron Technology, Inc. Isolated structure and method of fabricating such a structure on a substrate
US8110455B2 (en) 2008-01-31 2012-02-07 Nxp B.V. Semiconductor device and a method of manufacturing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112771A (en) * 1987-03-20 1992-05-12 Mitsubishi Denki Kabushiki Kaisha Method of fibricating a semiconductor device having a trench
JPS63271952A (en) * 1987-04-28 1988-11-09 Nec Corp Manufacture of semiconductor device
US6110798A (en) * 1996-01-05 2000-08-29 Micron Technology, Inc. Method of fabricating an isolation structure on a semiconductor substrate
US6465865B1 (en) 1996-01-05 2002-10-15 Micron Technology, Inc. Isolated structure and method of fabricating such a structure on a substrate
US6479370B2 (en) 1996-01-05 2002-11-12 Micron Technology, Inc. Isolated structure and method of fabricating such a structure on a substrate
US6559032B2 (en) 1996-01-05 2003-05-06 Micron Technology, Inc. Method of fabricating an isolation structure on a semiconductor substrate
US8110455B2 (en) 2008-01-31 2012-02-07 Nxp B.V. Semiconductor device and a method of manufacturing the same

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