CN105914138A - PIP (Poly-Insulator-Poly) capacitor process method - Google Patents
PIP (Poly-Insulator-Poly) capacitor process method Download PDFInfo
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- CN105914138A CN105914138A CN201610470548.1A CN201610470548A CN105914138A CN 105914138 A CN105914138 A CN 105914138A CN 201610470548 A CN201610470548 A CN 201610470548A CN 105914138 A CN105914138 A CN 105914138A
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- poly
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- silicon nitride
- oxide layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a PIP (Poly-Insulator-Poly) capacitor process method. The method comprises the following steps: 1, M-Poly is deposited on a shallow slot isolation structure and etched back; 2, deposition of an oxide layer and deposition of a layer of silicon nitride are then sequentially carried out on the M-Poly; 3, the silicon nitride is etched back, and the oxide layer is subjected to wet etching; 4, a high-voltage oxide layer is deposited; 5, slot gate polysilicon is deposited; and 6, the slot gate polysilicon is etched back. Through depositing the oxide layer and the silicon nitride to form a side wall to thicken the dielectric layer at the bottom end of the M-Poly side wall, the breakdown voltage is improved in a condition of almost not reducing capacitance, and leakage current is reduced.
Description
Technical field
The present invention relates to IC design and manufacture field, particularly relate to the process of a kind of PIP capacitor.
Background technology
Electric capacity is passive device conventional in IC chip, such as in a kind of E-Flash device (FS115), for
Cost-effective, use PIP capacitor (Poly-Insolator-Poly, polysilicondielectric layer-polysilicon, i.e.
M-Poly/HV Oxide/GT-Poly) cross-section structure as it is shown in figure 1, be a kind of up-down structure, shallow groove isolation structure
It is the one layer of M-Poly (i.e. Memory Poly, the memorizer storage tube polysilicon) bottom crown as PIP capacitor on STI,
M-Poly is upper be high-pressure oxidation layer (HV Oxide) as the insulating medium layer between capacitor plate, top crown is trench gate
Polysilicon (GT-Poly) is constituted, and forms PIP structure.Upper bottom crown is drawn by contact hole.
The manufacture method of this structure includes: M-Poly deposit and time quarter；High-pressure oxidation layer deposits；Trench gate polysilicon deposits；
Trench gate polysilicon returns quarter.The defect of this manufacturing process is: after M-Poly etches, electric capacity edge bottom can be formed
Most advanced and sophisticated space and have certain oxide layer loss, as shown in Figure 2, follow-up HV HTO Oxide is in this district
Territory is the thinnest, as it is shown on figure 3, after GT-Poly is formed, this region is easy for because pattern is the sharpest and Oxide
The thinnest cause punch through the problem that voltage is the most up to standard.
Summary of the invention
The technical problem to be solved is to provide the process of a kind of PIP capacitor, has higher breakdown potential
Pressure.
For solving the problems referred to above, the process of PIP capacitor of the present invention, comprise the steps of:
Step 1, deposits M-Poly on shallow groove isolation structure and returns quarter；
Step 2, carries out oxide layer deposit and the deposit of one layer of silicon nitride on M-Poly the most successively；
Step 3, returns and carves silicon nitride, wet etching oxide layer；
Step 4, deposits high-pressure oxidation layer；
Step 5, deposits trench gate polysilicon；
Step 6, trench gate polysilicon returns quarter.
In described step 1, the M-Poly thickness of deposit is
In described step 2, the oxidated layer thickness of deposit isThe silicon nitride thickness of deposit is
In described step 4, the high-pressure oxidation layer thickness of deposit is
In described step 5, the trench gate polysilicon thickness of deposit is
The process of PIP capacitor of the present invention, utilizes silicon oxide to form side wall with silicon nitride at M-Polyc sidewall,
Thicken the oxidated layer thickness of M-Ploy sidewall bottom, eliminate traditional handicraft and taper off to a point in M-Poly bottom and make oxygen
Change the problem that the thinning breakdown voltage caused of layer is on the low side.Technique is the most easy to implement.
Accompanying drawing explanation
Fig. 1 is the sectional structure chart of PIP capacitor.
Fig. 2 is the generalized section that PIP capacitor traditional handicraft M-Poly returns after quarter, tapers off to a point in sidewall bottom.
Fig. 3 is the section microstructure figure of PIP capacitor.
Fig. 4～9 is the processing step schematic diagram of PIP capacitor of the present invention.
Figure 10 is the processing step flow chart of PIP capacitor of the present invention.
Detailed description of the invention
The process of PIP capacitor of the present invention, comprises the steps of:
Step 1, on shallow groove isolation structure STI, deposition thickness isM-Poly and return carve, Dian Xinghou
Degree isAs shown in Figure 4.
Step 2, carries out oxide layer deposit and the deposit of one layer of silicon nitride on M-Poly the most successively；Oxidated layer thickness isThe silicon nitride thickness of deposit isThe present embodiment oxidated layer thickness valueSilicon nitride
Layer thickness valueAs shown in Figure 5.
Step 3, returns and carves silicon nitride, silicon nitride layer is done dry etching, silicon nitride layer and the nitrogen of logic area on surface
SiClx and portion of oxide layer etch away.Wet etching falls remaining oxide layer.Side wall is formed at M-Poly sidewall.Such as Fig. 6
Shown in.
Step 4, deposition thickness isHigh-pressure oxidation layer HV Oxide, such as deposition thickness isAs
Shown in Fig. 7.
Step 5, deposition thickness isTrench gate polysilicon GT-Poly, the present embodiment select thickness beAs shown in Figure 8.
Step 6, trench gate polysilicon GT-Poly returns quarter, and described PIP capacitor completes.It is finally completed such as Fig. 9
Shown in.
The embodiment of the present invention is by depositLeft and right oxide layer andThe silicon nitride of left and right forms side wall and thickens
The dielectric layer of M-Poly sidewall bottom, (only affects side capacitive, and side electricity in the case of reducing electric capacity hardly
Hold much smaller than front electric capacity) improve breakdown voltage, reduce leakage current.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art,
The present invention can have various modifications and variations.All within the spirit and principles in the present invention, any amendment of being made, equivalent
Replacement, improvement etc., should be included within the scope of the present invention.
Claims (5)
1. the process of a PIP capacitor, it is characterised in that: comprise the steps of:
Step 1, deposits M-Poly on shallow groove isolation structure and returns quarter；
Step 2, carries out oxide layer deposit and the deposit of one layer of silicon nitride on M-Poly the most successively；
Step 3, returns and carves silicon nitride, wet etching oxide layer；
Step 4, deposits high-pressure oxidation layer；
Step 5, deposits trench gate polysilicon；
Step 6, trench gate polysilicon returns quarter.
2. the process of PIP capacitor as claimed in claim 1, it is characterised in that: in described step 1, deposit
M-Poly thickness is
3. the process of PIP capacitor as claimed in claim 1, it is characterised in that: in described step 2, deposit
Oxidated layer thickness isThe silicon nitride thickness of deposit is
4. the process of PIP capacitor as claimed in claim 1, it is characterised in that: in described step 4, deposit
High-pressure oxidation layer thickness is
5. the process of PIP capacitor as claimed in claim 1, it is characterised in that: in described step 5, deposit
Trench gate polysilicon thickness is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610470548.1A CN105914138A (en) | 2016-06-24 | 2016-06-24 | PIP (Poly-Insulator-Poly) capacitor process method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610470548.1A CN105914138A (en) | 2016-06-24 | 2016-06-24 | PIP (Poly-Insulator-Poly) capacitor process method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105914138A true CN105914138A (en) | 2016-08-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610470548.1A Pending CN105914138A (en) | 2016-06-24 | 2016-06-24 | PIP (Poly-Insulator-Poly) capacitor process method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111293038A (en) * | 2020-02-25 | 2020-06-16 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
| FR3093591A1 (en) * | 2019-03-06 | 2020-09-11 | Stmicroelectronics (Rousset) Sas | Manufacturing process of a high voltage capacitive element, and corresponding integrated circuit |
| US11437406B2 (en) | 2019-12-20 | 2022-09-06 | Globalfoundries Singapore Pte. Ltd. | Semiconductor device having a capacitive structure and method of forming the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6481357A (en) * | 1987-09-24 | 1989-03-27 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| CN1220493A (en) * | 1997-12-19 | 1999-06-23 | 三菱电机株式会社 | Semiconductor device and manfacturing method thereof |
| CN101211844B (en) * | 2006-12-27 | 2010-09-22 | 东部高科股份有限公司 | Method for manufacturing semiconductor device |
| CN105632897A (en) * | 2016-02-23 | 2016-06-01 | 中航（重庆）微电子有限公司 | MIM (metal-insulator-metal) capacitor and preparation method therefor |
-
2016
- 2016-06-24 CN CN201610470548.1A patent/CN105914138A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6481357A (en) * | 1987-09-24 | 1989-03-27 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| CN1220493A (en) * | 1997-12-19 | 1999-06-23 | 三菱电机株式会社 | Semiconductor device and manfacturing method thereof |
| CN101211844B (en) * | 2006-12-27 | 2010-09-22 | 东部高科股份有限公司 | Method for manufacturing semiconductor device |
| CN105632897A (en) * | 2016-02-23 | 2016-06-01 | 中航（重庆）微电子有限公司 | MIM (metal-insulator-metal) capacitor and preparation method therefor |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3093591A1 (en) * | 2019-03-06 | 2020-09-11 | Stmicroelectronics (Rousset) Sas | Manufacturing process of a high voltage capacitive element, and corresponding integrated circuit |
| US11271075B2 (en) | 2019-03-06 | 2022-03-08 | Stmicroelectronics (Rousset) Sas | Process for fabricating a high-voltage capacitive element, and corresponding integrated circuit |
| US11640972B2 (en) | 2019-03-06 | 2023-05-02 | Stmicroelectronics (Rousset) Sas | Process for fabricating a high-voltage capacitive element, and corresponding integrated circuit |
| US11437406B2 (en) | 2019-12-20 | 2022-09-06 | Globalfoundries Singapore Pte. Ltd. | Semiconductor device having a capacitive structure and method of forming the same |
| CN111293038A (en) * | 2020-02-25 | 2020-06-16 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
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Application publication date: 20160831 |