CN102479746A - Method for reducing parasitic capacitance between metal gate electrode and contact hole - Google Patents

Method for reducing parasitic capacitance between metal gate electrode and contact hole Download PDF

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CN102479746A
CN102479746A CN2010105636640A CN201010563664A CN102479746A CN 102479746 A CN102479746 A CN 102479746A CN 2010105636640 A CN2010105636640 A CN 2010105636640A CN 201010563664 A CN201010563664 A CN 201010563664A CN 102479746 A CN102479746 A CN 102479746A
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layer
gate electrode
gate
metal gate
contact hole
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CN102479746B (en
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刘金华
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The invention provides a method for reducing a parasitic capacitance between a metal gate electrode and a contact hole. A replaced grate electrode is removed according to a rear gate electrode process to form a trench and side wall layers are manufactured at two sides in the trench in advance, wherein a certain distance is reserved between the metal gate electrode and the contact hole by the side wall layers; gate oxidization layers with a high dielectric constant at two sides of the metal gate electrode are removed together so that the gate oxidization layers with the high dielectric constant do not exist between the metal gate electrode and the contact hole, the parasitic capacitance is greatly reduced, and the defect that a signal of a semiconductor is delayed or the power consumption is increased is effectively overcome.

Description

Reduce the method for parasitic capacitance between metal gate electrode and the contact hole
Technical field
The present invention relates to semiconductor logic circuit and make field, particularly a kind of method that reduces parasitic capacitance between metal gate electrode and the contact hole.
Background technology
At present, high dielectric constant insulating material and metal gate electrode will be used to make logic circuit device.
In order to control short-channel effect, the smaller szie requirement on devices further improves gate electrode electric capacity.This can realize through the thickness of continuous attenuate gate oxide, but the thing followed is the lifting of gate electrode leakage current.When silicon dioxide as gate oxide, when thickness was lower than 5.0 nanometers, leakage current just became and can't stand.Solution to the problems described above just is to use high dielectric constant insulating material to replace silicon dioxide; High dielectric constant insulating material can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc.; Dielectric constant is generally all greater than 15; Adopt this material can further improve gate capacitance, gate leak current can be significantly improved again simultaneously.For identical gate oxide thickness; With high dielectric constant insulating material and metal gate electrode collocation; Its gate electrode leakage current will reduce several index magnitudes, and solve problem incompatible between high dielectric constant insulating material and the polysilicon with metal gate electrode replacement polygate electrodes.
The method of grid technology making metal gate electrode may further comprise the steps after the prior art utilization, describes below in conjunction with Fig. 1 a to Fig. 1 e.
Step 11, shown in Fig. 1 a, on the active area 101 of Semiconductor substrate 100, form boundary layer 102 and polysilicon gate 103 successively.Wherein, boundary layer 102 is generally silicon oxide layer as thin as a wafer, perhaps silicon oxynitride layer.
Step 12, shown in Fig. 1 b, on the surface of Semiconductor substrate 100, be not formed with the position deposition interlayer dielectric layer (ILD) 104 of boundary layer 102 and polysilicon gate 103, the height of said interlayer dielectric layer 104 depositions flushes with polysilicon gate 103.The material of interlayer dielectric layer is generally silicon oxide layer.
Step 13, shown in Fig. 1 c, polysilicon gate 103 removed from the interlayer dielectric layer 104 of burying forms groove.The general wet method (wet clean) that adopts is removed, and specifically adopts the acid of nitric acid and hydrogen peroxide solution to dissolve and removes.
Step 14, shown in Fig. 1 d; Deposition has the gate oxide of high-k and the material of metal gate electrode successively; This gate oxide with high-k also can cover the surface of interlayer dielectric layer 104 during deposition; The metal gate electrode material covers the gate oxide surface with high-k, then through cmp (CMP), metal gate electrode material and the gate oxide with high-k is polished successively; To manifesting interlayer dielectric layer 104, have the gate oxide 105 and metal gate electrode 106 of high-k with formation.Wherein, the material as metal gate electrode can be any two kinds of perhaps three kinds the combinations in titanium (Ti), titanium nitride (TiN), tantalum (Ta), the tantalum nitride (TaN).
Step 15, shown in Fig. 1 e, above the both sides of metal gate electrode 106 active area 101, interlayer dielectric layer 104 is carried out etching, form contact hole (CT) 107.Contact hole behind the filling metal is used for carrying out electrical interconnects with the metal interconnecting layer of last part technology.
It should be noted that; Can find out from Fig. 1 e; The gate oxide 105 and interlayer dielectric layer 104 that between contact hole 107 and metal gate electrode 106, have high-k, and the gate oxide 105 of high-k is because its high dielectric constant has increased the parasitic capacitance between contact hole 107 and the metal gate electrode 106 greatly.The defective that therefore can cause formed semiconductor device signal delay or power consumption to increase.
Summary of the invention
In view of this, the technical problem of the present invention's solution is: how to reduce the parasitic capacitance between contact hole and the metal gate electrode.
For solving the problems of the technologies described above, technical scheme of the present invention specifically is achieved in that
The invention discloses a kind of method that reduces parasitic capacitance between metal gate electrode and the contact hole, this method comprises:
On active area of semiconductor substrate, form boundary layer and replacement gate successively;
On the surface of Semiconductor substrate, be not formed with the position deposition interlayer dielectric layer of boundary layer and replacement gate;
Replacement gate is removed the formation groove from the interlayer dielectric layer of burying;
Deposition has the gate oxide of high-k; Said bottom, sidewall and outside with gate oxide covering groove of high-k;
Formation is attached to the inner side walls layer of groove on the gate oxide surface with high-k;
The plated metal gate material, and said metal gate electrode material and the gate oxide with high-k carried out cmp, to manifesting interlayer dielectric layer, form metal gate electrode;
Etching is positioned at the gate oxide with high-k of said trenched side-wall and the interlayer dielectric layer that is in contact with it, and forms the contact hole that contacts with active area.
Said side wall layer is a silicon nitride layer.
This method further comprises: after deposition had the gate oxide of high-k, formation was attached to before the groove side walls layer, in the step of the gate oxide surface deposition silicon oxide layer with high-k;
After formation is attached to groove side walls layer, before the plated metal gate material, said silicon oxide layer is carried out etching, to the step that manifests gate oxide with high-k.
Said side wall layer is a silicon oxide layer.
Said boundary layer is silicon oxide layer or silicon oxynitride layer.
Said replacement gate is a polysilicon gate.
Said interlayer dielectric layer is a silicon oxide layer.
Visible by above-mentioned technical scheme; What the present invention was crucial is to make side wall layer in the both sides, inside of groove in advance; This side wall layer is with metal gate electrode and the spaced apart certain distance of contact hole; So just can be when the etching contact hole, the gate oxide that will be positioned at the high-k of metal gate electrode both sides is together removed, so between metal gate electrode and the contact hole owing to no longer there is the gate oxide of high-k; So parasitic capacitance significantly reduces, effectively overcome the defective that formed semiconductor device signal delay or power consumption increase.
Description of drawings
Fig. 1 a to 1e utilizes the back grid technology to make the structural representation of the detailed process of metal gate electrode in the prior art.
Fig. 2 is the method flow diagram of the preferred embodiment of the present invention for parasitic capacitance between minimizing metal gate electrode and the contact hole.
Fig. 2 a to Fig. 2 h is the present invention and the corresponding concrete structure sketch map of Fig. 2 method.
Embodiment
For make the object of the invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
The present invention utilizes sketch map to describe in detail; When the embodiment of the invention was detailed, for the ease of explanation, the sketch map of expression structure can be disobeyed general ratio and done local the amplification; Should be with this as to qualification of the present invention; In addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
The preferred embodiment of the present invention is as shown in Figure 2 for the method flow diagram that reduces parasitic capacitance between metal gate electrode and the contact hole, is elaborated below in conjunction with Fig. 2 a to Fig. 2 h, and it may further comprise the steps:
Step 21, shown in Fig. 2 a, on the active area 101 of Semiconductor substrate 100, form boundary layer 102 and polysilicon gate 103 successively.Wherein, boundary layer 102 is generally silicon oxide layer as thin as a wafer, perhaps silicon oxynitride layer.
Need to prove; Because final formation is metal gate electrode; Polysilicon gate 103 can be substituted by metal gate electrode; That is to say that polysilicon gate 103 finally is non-existent, so can have multiplely as the material of the replacement gate of polysilicon gate, the material of replacement gate is a polysilicon in the embodiment of the invention.
Step 22, shown in Fig. 2 b, on the surface of Semiconductor substrate 100, be not formed with the position deposition interlayer dielectric layer (ILD) 104 of boundary layer 102 and polysilicon gate 103, the height of said interlayer dielectric layer 104 depositions flushes with polysilicon gate 103.The material of interlayer dielectric layer is generally silicon oxide layer.
Step 23, shown in Fig. 2 c, polysilicon gate 103 removed from the interlayer dielectric layer 104 of burying forms groove.The general wet method (wet clean) that adopts is removed, and specifically adopts the acid of nitric acid and hydrogen peroxide solution to dissolve and removes.
Step 24, shown in Fig. 2 d, deposition has gate oxide 205, silicon oxide layer 206 and the silicon nitride layer 207 of high-k, said bottom, sidewall and outside with gate oxide 205 covering grooves of high-k successively.
Wherein, High dielectric constant insulating material can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc.; Dielectric constant is generally all greater than 15; According to common practise, because its dielectric constant than the common gate oxide that is made up of silica is high a lot, so be referred to as to have the gate oxide of high-k.
Step 25, shown in Fig. 2 e, said silicon nitride layer 207 is carried out anisotropic etching, form the silicon nitride sidewall layer 207 ' of the inner both sides of groove be attached to the silicon oxide layer surface.Forming silicon nitride sidewall layer 207 ' is committed step of the present invention, and this side wall layer is with the spaced apart certain distance of the contact hole of metal gate electrode and follow-up formation.
Step 26, shown in Fig. 2 f, said silicon oxide layer 206 is carried out etching, to manifesting gate oxide with high-k.At this moment, silicon oxide layer 206 is not capped part and all removes after over etching, keeps the partial oxidation silicon layer 206 ' that is positioned at trenched side-wall and bottom.The main purpose of this step is for follow-up metal gate electrode to be contacted with the gate oxide with high-k.
Step 27, shown in Fig. 2 g, plated metal gate material, and said metal gate electrode material and the gate oxide 205 with high-k carried out cmp to manifesting interlayer dielectric layer 104, forms metal gate electrode 208.
Wherein, The metal gate electrode material that is deposited can be filled completely whole groove, and covers the gate oxide surface with high-k, through after the cmp; Gate oxide 205 with high-k is ground simultaneously; Form polished gate oxide 205 ' with high-k, originally the outside gate oxide with high-k of covering groove is ground removal, keeps the gate oxide with high-k of trenched side-wall and bottom.Material as metal gate electrode can be any two kinds of perhaps three kinds the combinations in titanium (Ti), titanium nitride (TiN), tantalum (Ta), the tantalum nitride (TaN).
Step 28, shown in Fig. 2 h, etching is positioned at the gate oxide with high-k of said trenched side-wall and the interlayer dielectric layer that is in contact with it, and forms the contact hole 209 contact with active area.Contact hole behind the filling metal is used for carrying out electrical interconnects with the metal interconnecting layer of last part technology.
Since the gate oxide with high-k only with plane that metal gate electrode contacts on work; And form inevitably during the said part deposition that is positioned at trenched side-wall; So method of the present invention forms in the process of contact hole in this step; Just the gate oxide with high-k of trenched side-wall is removed; The gate oxide with high-k 205 that contacts with metal gate electrode that keeps channel bottom ", solved the big problem of parasitic capacitance between contact hole and the metal gate electrode.And the technology of prior art is impossible in this step, directly the gate oxide with high-k of trenched side-wall to be removed; This be because prior art in shown in Fig. 1 d; Metal gate electrode directly contacts with the gate oxide with high-k; Distance is too near, during the etching contact hole, and can only the etching interlayer dielectric layer.
Need to prove that in step 24, the purpose of silicon oxide layer deposited 206 is to reduce the stress of the silicon nitride layer 207 that is deposited; According to common practise, the stress ratio that silicon nitride layer forms is bigger, can cause damage to the material layer below it; So silicon oxide layer deposited of the present invention 206 is mainly as resilient coating; Protect other layers injury-free, and the silicon oxide layer of trenched side-wall can together be removed in step 28, only keeps the silicon oxide layer 206 that is positioned at channel bottom in the process of etching contact hole "; this silicon oxide layer 206 " do not play any function, can not hinder the work of formed semiconductor device yet.
For clear description the present invention, omitted a plurality of processing steps such as for example ion injection in the method for the invention, this is a common practise, repeats no more.
According to foregoing description, the deposition of silicon oxide layer 206 is not necessary, if only silicon nitride layer 207 also can be realized the object of the invention as side wall layer, just effect is not best, thus above-mentioned be the preferred embodiments of the present invention.In addition, also can be only with silicon oxide layer as side wall layer, thereby realize the object of the invention.To sum up, the invention provides a kind of method that reduces parasitic capacitance between metal gate electrode and the contact hole, this method comprises:
On active area of semiconductor substrate, form boundary layer and replacement gate successively;
On the surface of Semiconductor substrate, be not formed with the position deposition interlayer dielectric layer of boundary layer and replacement gate;
Replacement gate is removed the formation groove from the interlayer dielectric layer of burying;
Deposition has the gate oxide of high-k; Said bottom, sidewall and outside with gate oxide covering groove of high-k;
Formation is attached to the inner side walls layer of groove on the gate oxide surface with high-k; Said side wall layer is silicon oxide layer or silicon nitride layer;
The plated metal gate material, and said metal gate electrode material and the gate oxide with high-k carried out cmp, to manifesting interlayer dielectric layer, form metal gate electrode;
Etching is positioned at the gate oxide with high-k of said trenched side-wall and the interlayer dielectric layer that is in contact with it, and forms the contact hole that contacts with active area.
Need to prove; Method of the present invention forms side wall layer in the inner both sides of groove; Can occupy certain size,, then can cause the size decreases of metal gate electrode in the groove if groove width is still identical with prior art; So if form the metal gate electrode with the prior art same size, then with wideer the getting final product in groove width etching ground.Through method of the present invention, reduced the parasitic capacitance between metal gate electrode and the contact hole, effectively overcome the defective that formed semiconductor device signal delay or power consumption increase.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope that the present invention protects.

Claims (7)

1. method that reduces parasitic capacitance between metal gate electrode and the contact hole, this method comprises:
On active area of semiconductor substrate, form boundary layer and replacement gate successively;
On the surface of Semiconductor substrate, be not formed with the position deposition interlayer dielectric layer of boundary layer and replacement gate;
Replacement gate is removed the formation groove from the interlayer dielectric layer of burying;
Deposition has the gate oxide of high-k; Said bottom, sidewall and outside with gate oxide covering groove of high-k;
Formation is attached to the inner side walls layer of groove on the gate oxide surface with high-k;
The plated metal gate material, and said metal gate electrode material and the gate oxide with high-k carried out cmp, to manifesting interlayer dielectric layer, form metal gate electrode;
Etching is positioned at the gate oxide with high-k of said trenched side-wall and the interlayer dielectric layer that is in contact with it, and forms the contact hole that contacts with active area.
2. the method for claim 1 is characterized in that, said side wall layer is a silicon nitride layer.
3. method as claimed in claim 2; It is characterized in that; This method further comprises: after deposition had the gate oxide of high-k, formation was attached to before the groove side walls layer, in the step of the gate oxide surface deposition silicon oxide layer with high-k;
After formation is attached to groove side walls layer, before the plated metal gate material, said silicon oxide layer is carried out etching, to the step that manifests gate oxide with high-k.
4. the method for claim 1 is characterized in that, said side wall layer is a silicon oxide layer.
5. the method for claim 1 is characterized in that, said boundary layer is silicon oxide layer or silicon oxynitride layer.
6. the method for claim 1 is characterized in that, said replacement gate is a polysilicon gate.
7. the method for claim 1 is characterized in that, said interlayer dielectric layer is a silicon oxide layer.
CN2010105636640A 2010-11-29 2010-11-29 Method for reducing parasitic capacitance between metal gate electrode and contact hole Active CN102479746B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102779852A (en) * 2012-07-18 2012-11-14 电子科技大学 SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure
CN109427653A (en) * 2017-08-31 2019-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6406945B1 (en) * 2001-01-26 2002-06-18 Chartered Semiconductor Manufacturing Ltd. Method for forming a transistor gate dielectric with high-K and low-K regions
CN101626022A (en) * 2008-07-09 2010-01-13 恩益禧电子股份有限公司 Semiconductor device and method of manufacturing the same
US20100025775A1 (en) * 2008-07-30 2010-02-04 Martin Giles Replacement spacers for mosfet fringe capacatance reduction and processes of making same
CN101681841A (en) * 2007-06-27 2010-03-24 国际商业机器公司 High-k/metal gate mosfet with reduced parasitic capacitance

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6406945B1 (en) * 2001-01-26 2002-06-18 Chartered Semiconductor Manufacturing Ltd. Method for forming a transistor gate dielectric with high-K and low-K regions
CN101681841A (en) * 2007-06-27 2010-03-24 国际商业机器公司 High-k/metal gate mosfet with reduced parasitic capacitance
CN101626022A (en) * 2008-07-09 2010-01-13 恩益禧电子股份有限公司 Semiconductor device and method of manufacturing the same
US20100025775A1 (en) * 2008-07-30 2010-02-04 Martin Giles Replacement spacers for mosfet fringe capacatance reduction and processes of making same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102779852A (en) * 2012-07-18 2012-11-14 电子科技大学 SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure
CN102779852B (en) * 2012-07-18 2014-09-10 电子科技大学 SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure
CN109427653A (en) * 2017-08-31 2019-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN109427653B (en) * 2017-08-31 2020-10-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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