CN102479746B - Method for reducing parasitic capacitance between metal gate electrode and contact hole - Google Patents

Method for reducing parasitic capacitance between metal gate electrode and contact hole Download PDF

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CN102479746B
CN102479746B CN2010105636640A CN201010563664A CN102479746B CN 102479746 B CN102479746 B CN 102479746B CN 2010105636640 A CN2010105636640 A CN 2010105636640A CN 201010563664 A CN201010563664 A CN 201010563664A CN 102479746 B CN102479746 B CN 102479746B
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gate
gate electrode
metal gate
interlayer dielectric
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CN102479746A (en
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刘金华
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

The invention provides a method for reducing a parasitic capacitance between a metal gate electrode and a contact hole. A replaced grate electrode is removed according to a rear gate electrode process to form a trench and side wall layers are manufactured at two sides in the trench in advance, wherein a certain distance is reserved between the metal gate electrode and the contact hole by the side wall layers; gate oxidization layers with a high dielectric constant at two sides of the metal gate electrode are removed together so that the gate oxidization layers with the high dielectric constant do not exist between the metal gate electrode and the contact hole, the parasitic capacitance is greatly reduced, and the defect that a signal of a semiconductor is delayed or the power consumption is increased is effectively overcome.

Description

Reduce the method for parasitic capacitance between metal gate electrode and contact hole
Technical field
The present invention relates to semiconductor logic circuit and make field, particularly a kind of method that reduces parasitic capacitance between metal gate electrode and contact hole.
Background technology
At present, high dielectric constant insulating material and metal gate electrode will be used to make logic circuit device.
In order to control short-channel effect, the smaller szie requirement on devices further improves gate electrode electric capacity.This can realize by the thickness of continuous attenuate gate oxide, but the thing followed is the lifting of gate electrode leakage current.As gate oxide, thickness is during lower than 5.0 nanometer when silicon dioxide, and leakage current just becomes and can't stand.Solution to the problems described above uses high dielectric constant insulating material to replace silicon dioxide exactly, high dielectric constant insulating material can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc., dielectric constant is generally all greater than 15, adopt this material can further improve gate capacitance, gate leak current can be significantly improved again simultaneously.For identical gate oxide thickness, with high dielectric constant insulating material and metal gate electrode collocation, its gate electrode leakage current will reduce several index magnitudes, and with metal gate electrode replacement polygate electrodes, solve problem incompatible between high dielectric constant insulating material and polysilicon.
After the prior art utilization, the method for grid technology making metal gate electrode comprises the following steps, and below in conjunction with Fig. 1 a to Fig. 1 e, describes.
Step 11, as shown in Figure 1a, form boundary layer 102 and polysilicon gate 103 successively on the active area 101 of Semiconductor substrate 100.Wherein, boundary layer 102 as thin as a wafer, is generally silicon oxide layer, perhaps silicon oxynitride layer.
Step 12, as shown in Figure 1 b, on the surface of Semiconductor substrate 100, be not formed with the position deposition interlayer dielectric layer (ILD) 104 of boundary layer 102 and polysilicon gate 103, and the height of described interlayer dielectric layer 104 depositions flushes with polysilicon gate 103.The material of interlayer dielectric layer is generally silicon oxide layer.
Step 13, as shown in Fig. 1 c, polysilicon gate 103 is removed form groove from the interlayer dielectric layer 104 of burying.The general wet method (wet clean) that adopts is removed, and specifically adopts nitric acid and hydrogen peroxide acid to dissolve and removes.
Step 14, as shown in Fig. 1 d, deposition has the gate oxide of high-k and the material of metal gate electrode successively, during deposition, this gate oxide with high-k also can cover the surface of interlayer dielectric layer 104, the metal gate electrode material covers the gate oxide surface with high-k, then by cmp (CMP), metal gate electrode material and the gate oxide with high-k are carried out polishing successively,, to manifesting interlayer dielectric layer 104, have gate oxide 105 and the metal gate electrode 106 of high-k with formation.Wherein, can be the combination of any two kinds or three kinds in titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) as the material of metal gate electrode.
Step 15, as shown in Fig. 1 e, above the both sides of metal gate electrode 106 active area 101, interlayer dielectric layer 104 is carried out etching, form contact hole (CT) 107.Contact hole after the filling metal is used for carrying out electrical interconnects with the metal interconnecting layer of last part technology.
It should be noted that, can find out from Fig. 1 e, have gate oxide 105 and the interlayer dielectric layer 104 of high-k between contact hole 107 and metal gate electrode 106, and the gate oxide 105 of high-k is because its high dielectric constant has increased parasitic capacitance between contact hole 107 and metal gate electrode 106 greatly.The defect that therefore can cause formed semiconductor device signal delay or power consumption to increase.
Summary of the invention
In view of this, the technical problem of the present invention's solution is: how to reduce the parasitic capacitance between contact hole and metal gate electrode.
For solving the problems of the technologies described above, technical scheme of the present invention specifically is achieved in that
The invention discloses a kind of method that reduces parasitic capacitance between metal gate electrode and contact hole, the method comprises:
Form successively boundary layer and replacement gate on the active area of Semiconductor substrate;
On the surface of Semiconductor substrate, be not formed with the position deposition interlayer dielectric layer of boundary layer and replacement gate;
Replacement gate is removed form groove from the interlayer dielectric layer of burying;
Deposition has the gate oxide of high-k; Described bottom, sidewall and outside with gate oxide covering groove of high-k;
Formation is attached to the side wall layer of the inner both sides of groove on the gate oxide surface with high-k;
The plated metal gate material, and described metal gate electrode material and the gate oxide with high-k are carried out cmp,, to manifesting interlayer dielectric layer, form metal gate electrode;
Etching is positioned at the gate oxide with high-k of described trenched side-wall and the interlayer dielectric layer that is in contact with it, and forms the contact hole that contacts with active area.
Described side wall layer is silicon nitride layer.
The method further comprises: after deposition has the gate oxide of high-k, before formation is attached to the side wall layer of groove both sides, in the step of the gate oxide surface deposition silicon oxide layer with high-k;
After formation is attached to the side wall layer of groove both sides, before the plated metal gate material, described silicon oxide layer is carried out etching, to the step that manifests the gate oxide with high-k.
Described side wall layer is silicon oxide layer.
Described boundary layer is silicon oxide layer or silicon oxynitride layer.
Described replacement gate is polysilicon gate.
Described interlayer dielectric layer is silicon oxide layer.
As seen from the above technical solutions, key of the present invention be to make in advance side wall layer in the both sides, inside of groove, this side wall layer is with metal gate electrode and the spaced apart certain distance of contact hole, so just can be when the etching contact hole, the gate oxide that will be positioned at the high-k of metal gate electrode both sides is together removed, therefore between metal gate electrode and contact hole due to the gate oxide that no longer has high-k,, so parasitic capacitance greatly reduces, effectively overcome the defect that formed semiconductor device signal delay or power consumption increase.
Description of drawings
Fig. 1 a to 1e is that after utilizing in prior art, grid technology is made the structural representation of the detailed process of metal gate electrode.
Fig. 2 is that the preferred embodiment of the present invention is to reduce the method flow diagram of parasitic capacitance between metal gate electrode and contact hole.
Fig. 2 a to Fig. 2 h is the present invention's concrete structure schematic diagram corresponding with Fig. 2 method.
Embodiment
For make purpose of the present invention, technical scheme, and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
The present invention utilizes schematic diagram to describe in detail, when the embodiment of the present invention is described in detail in detail, for convenience of explanation, the schematic diagram of expression structure can be disobeyed general ratio and be done local the amplification, should not use this as limitation of the invention, in addition, in the making of reality, should comprise the three-dimensional space of length, width and the degree of depth.
The preferred embodiment of the present invention for the method flow diagram that reduces parasitic capacitance between metal gate electrode and contact hole as shown in Figure 2, be elaborated below in conjunction with Fig. 2 a to Fig. 2 h, it comprises the following steps:
Step 21, as shown in Figure 2 a, form boundary layer 102 and polysilicon gate 103 successively on the active area 101 of Semiconductor substrate 100.Wherein, boundary layer 102 as thin as a wafer, is generally silicon oxide layer, perhaps silicon oxynitride layer.
Need to prove, because final formation is metal gate electrode, polysilicon gate 103 can be substituted by metal gate electrode, that is to say that polysilicon gate 103 is finally non-existent, so can have multiplely as the material of the replacement gate of polysilicon gate, in the embodiment of the present invention, the material of replacement gate is polysilicon.
Step 22, as shown in Figure 2 b, on the surface of Semiconductor substrate 100, be not formed with the position deposition interlayer dielectric layer (ILD) 104 of boundary layer 102 and polysilicon gate 103, and the height of described interlayer dielectric layer 104 depositions flushes with polysilicon gate 103.The material of interlayer dielectric layer is generally silicon oxide layer.
Step 23, as shown in Figure 2 c, remove polysilicon gate 103 and form groove from the interlayer dielectric layer 104 of burying.The general wet method (wet clean) that adopts is removed, and specifically adopts nitric acid and hydrogen peroxide acid to dissolve and removes.
Step 24, as shown in Figure 2 d, deposition has gate oxide 205, silicon oxide layer 206 and the silicon nitride layer 207 of high-k, described bottom, sidewall and outside with gate oxide 205 covering grooves of high-k successively.
Wherein, high dielectric constant insulating material can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc., dielectric constant is generally all greater than 15, according to common practise, because they are high more a lot of than the dielectric constant of the common gate oxide that consists of silica, so be referred to as to have the gate oxide of high-k.
Step 25, as shown in Fig. 2 e, described silicon nitride layer 207 is carried out anisotropic etching, form the silicon nitride sidewall layer 207 ' of the inner both sides of groove be attached to the silicon oxide layer surface.Forming silicon nitride sidewall layer 207 ' is committed step of the present invention, and this side wall layer is with the spaced apart certain distance of the contact hole of metal gate electrode and follow-up formation.
Step 26, as shown in Fig. 2 f, described silicon oxide layer 206 is carried out etching, to manifesting the gate oxide with high-k.At this moment, silicon oxide layer 206 is after over etching, and not capped part is all removed, and keeps the partial oxidation silicon layer 206 ' that is positioned at trenched side-wall and bottom.The main purpose of this step is for follow-up, metal gate electrode to be contacted with the gate oxide with high-k.
Step 27, as shown in Figure 2 g, the plated metal gate material, and described metal gate electrode material and gate oxide 205 with high-k are carried out cmp,, to manifesting interlayer dielectric layer 104, form metal gate electrode 208.
Wherein, the metal gate electrode material that deposits can be filled completely whole groove, and it is surperficial to cover the gate oxide with high-k, through after cmp, gate oxide 205 with high-k is polished simultaneously, form polished gate oxide 205 ' with high-k, originally the gate oxide with high-k of covering groove outside is removed, and keeps the gate oxide with high-k of trenched side-wall and bottom.Can be the combination of any two kinds or three kinds in titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) as the material of metal gate electrode.
Step 28, as shown in Fig. 2 h, etching is positioned at the gate oxide with high-k of described trenched side-wall and the interlayer dielectric layer that is in contact with it, and forms the contact hole 209 contact with active area.Contact hole after the filling metal is used for carrying out electrical interconnects with the metal interconnecting layer of last part technology.
Because the gate oxide with high-k only works on the plane with metal gate electrode contacts, and inevitably form during the described part deposition that is positioned at trenched side-wall, so method of the present invention forms in the process of contact hole in this step, just the gate oxide with high-k of trenched side-wall is removed, the gate oxide with high-k 205 that contacts with metal gate electrode that keeps channel bottom ", solved the large problem of parasitic capacitance between contact hole and metal gate electrode.And the technique of prior art is impossible directly the gate oxide with high-k of trenched side-wall to be removed in this step, this be because prior art in as shown in Fig. 1 d, metal gate electrode directly contacts with the gate oxide with high-k, distance is too near, during the etching contact hole, can only the etching interlayer dielectric layer.
need to prove, in step 24, the purpose of silicon oxide layer deposited 206 is to reduce the stress of the silicon nitride layer 207 that deposits, according to common practise, the stress ratio that silicon nitride layer forms is larger, can be to the material layer injury below it, so silicon oxide layer deposited 206 of the present invention is mainly as resilient coating, protect other layers injury-free, and the silicon oxide layer of trenched side-wall can together be removed in the process of etching contact hole in step 28, only keep the silicon oxide layer 206 that is positioned at channel bottom ", this silicon oxide layer 206 " do not play any function, also can not hinder the work of formed semiconductor device.
For clear description the present invention, omitted in the method for the invention such as a plurality of processing steps such as Implantations, this is common practise, repeats no more.
According to foregoing description, the deposition of silicon oxide layer 206 is not necessary, if only silicon nitride layer 207 also can be realized purpose of the present invention as side wall layer, just effect is not best, thus above-mentioned be the preferred embodiments of the present invention.In addition, also can be only with silicon oxide layer as side wall layer, thereby realize purpose of the present invention.To sum up, the invention provides a kind of method that reduces parasitic capacitance between metal gate electrode and contact hole, the method comprises:
Form successively boundary layer and replacement gate on the active area of Semiconductor substrate;
On the surface of Semiconductor substrate, be not formed with the position deposition interlayer dielectric layer of boundary layer and replacement gate;
Replacement gate is removed form groove from the interlayer dielectric layer of burying;
Deposition has the gate oxide of high-k; Described bottom, sidewall and outside with gate oxide covering groove of high-k;
Formation is attached to the side wall layer of the inner both sides of groove on the gate oxide surface with high-k; Described side wall layer is silicon oxide layer or silicon nitride layer;
The plated metal gate material, and described metal gate electrode material and the gate oxide with high-k are carried out cmp,, to manifesting interlayer dielectric layer, form metal gate electrode;
Etching is positioned at the gate oxide with high-k of described trenched side-wall and the interlayer dielectric layer that is in contact with it, and forms the contact hole that contacts with active area.
Need to prove, method of the present invention forms side wall layer in the inner both sides of groove, can occupy certain size, if groove width is still same as the prior art, the size decreases that can cause metal gate electrode in groove, so if form the metal gate electrode of size same as the prior art, with wider the getting final product in groove width etching ground.By method of the present invention, reduced the parasitic capacitance between metal gate electrode and contact hole, effectively overcome the defect that formed semiconductor device signal delay or power consumption increase.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.

Claims (7)

1. method that reduces parasitic capacitance between metal gate electrode and contact hole, the method comprises:
Form successively boundary layer and replacement gate on the active area of Semiconductor substrate;
On the surface of Semiconductor substrate, be not formed with the position deposition interlayer dielectric layer of boundary layer and replacement gate;
Replacement gate is removed form groove from the interlayer dielectric layer of burying;
Deposition has the gate oxide of high-k; Bottom, the sidewall of described gate oxide covering groove with high-k also covers the interlayer dielectric layer surface;
Formation is attached to the side wall layer of the inner both sides of groove on the gate oxide surface with high-k;
The plated metal gate material, and described metal gate electrode material and the gate oxide with high-k are carried out cmp,, to manifesting interlayer dielectric layer, form metal gate electrode;
Etching is positioned at the gate oxide with high-k of described trenched side-wall and the interlayer dielectric layer that is in contact with it, and forms the contact hole that contacts with active area.
2. the method for claim 1, is characterized in that, described side wall layer is silicon nitride layer.
3. method as claimed in claim 2, it is characterized in that, the method further comprises: after deposition has the gate oxide of high-k, before forming the side wall layer that is attached to the inner both sides of groove, in the step of the gate oxide surface deposition silicon oxide layer with high-k;
After formation is attached to the side wall layer of groove both sides, before the plated metal gate material, described silicon oxide layer is carried out etching, to the step that manifests the gate oxide with high-k.
4. the method for claim 1, is characterized in that, described side wall layer is silicon oxide layer.
5. the method for claim 1, is characterized in that, described boundary layer is silicon oxide layer or silicon oxynitride layer.
6. the method for claim 1, is characterized in that, described replacement gate is polysilicon gate.
7. the method for claim 1, is characterized in that, described interlayer dielectric layer is silicon oxide layer.
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CN102779852B (en) * 2012-07-18 2014-09-10 电子科技大学 SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure
CN109427653B (en) * 2017-08-31 2020-10-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Citations (3)

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Publication number Priority date Publication date Assignee Title
US6406945B1 (en) * 2001-01-26 2002-06-18 Chartered Semiconductor Manufacturing Ltd. Method for forming a transistor gate dielectric with high-K and low-K regions
CN101626022A (en) * 2008-07-09 2010-01-13 恩益禧电子股份有限公司 Semiconductor device and method of manufacturing the same
CN101681841A (en) * 2007-06-27 2010-03-24 国际商业机器公司 High-k/metal gate mosfet with reduced parasitic capacitance

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US7838373B2 (en) * 2008-07-30 2010-11-23 Intel Corporation Replacement spacers for MOSFET fringe capacitance reduction and processes of making same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6406945B1 (en) * 2001-01-26 2002-06-18 Chartered Semiconductor Manufacturing Ltd. Method for forming a transistor gate dielectric with high-K and low-K regions
CN101681841A (en) * 2007-06-27 2010-03-24 国际商业机器公司 High-k/metal gate mosfet with reduced parasitic capacitance
CN101626022A (en) * 2008-07-09 2010-01-13 恩益禧电子股份有限公司 Semiconductor device and method of manufacturing the same

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