CN102646589A - Manufacturing method of MOSFET (metal-oxide-semiconductor field effect transistor) - Google Patents

Manufacturing method of MOSFET (metal-oxide-semiconductor field effect transistor) Download PDF

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CN102646589A
CN102646589A CN201110039626XA CN201110039626A CN102646589A CN 102646589 A CN102646589 A CN 102646589A CN 201110039626X A CN201110039626X A CN 201110039626XA CN 201110039626 A CN201110039626 A CN 201110039626A CN 102646589 A CN102646589 A CN 102646589A
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sacrificial
gate
manufacturing
dielectric layer
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CN102646589B (en
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李凡
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中芯国际集成电路制造(上海)有限公司
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Abstract

The invention provides a manufacturing method of an MOSFET (metal-oxide-semiconductor field effect transistor). The manufacturing method is characterized in that a sacrificial side wall of amorphous carbon is removed by adopting oxygen or carbon dioxide plasma oxidation method to form a side wall hole; and the dielectric constant of the side wall hole is 1 and is only one seventh of a silicon nitride side wall, so that the capacitance between the grid and a contact plug of a source-drain region can be obviously reduced, and the speed and the switching power consumption performance of a short-grid-length MOSFET device can be effectively improved. The manufacturing method provided by the invention has the advantages that the process is simple, the cost is saved, the formed side wall cavity can exist permanently, and the service life of the device can be prolonged.

Description

—种MOSFET制造方法 - kind of MOSFET manufacturing method

技术领域 FIELD

[0001] 本发明涉及半导体制造领域,尤其涉及ー种MOSFET的制造方法。 [0001] The present invention relates to semiconductor manufacturing, and more particularly relates to a method of manufacturing a MOSFET ー species.

背景技术 Background technique

[0002] 当栅极长度较短吋,MOSFET(金属氧化物半导体场效应管)的电容主要来源于栅极与源漏区接触插塞之间的电容,降低这个电容,可以有效提高短栅长MOSFET器件的速度和开关功耗性能。 [0002] When the gate length is shorter inch, the MOSFET (metal-oxide semiconductor) capacitor from the main gate and the source and drain regions of the contact between the plug capacitor, the capacitance decrease, can effectively improve the short gate length switching speed and power performance of the MOSFET device. 要降低栅极与源漏区接触插塞之间的电容,最有效的方法是降低栅极与源漏区之间的介电常数。 A method to reduce the source and drain regions and a gate capacitance between the contact plug is inserted, the most effective to reduce the dielectric constant between the gate and the source and drain regions.

[0003] 目前高密度MOSFET存储器件制造一般采用自对准接触(self-alignedcontact,SAC)技术下的氮化硅侧墙结构来实现,氮化硅侧墙的介电常数较大(K = 7),可以有效防止高浓度源漏区离子注入进入沟道,避免自对准硅化物电极形成过程中栅极与源漏区之间的短路。 [0003] It MOSFET high density memory devices generally used for producing self-aligned contact (self-alignedcontact, SAC) structure in the silicon nitride spacers technology to achieve, a larger dielectric constant of silicon nitride spacers (K = 7 ), can effectively prevent the high-concentration source drain ion implantation into the channel region, the salicide electrode to avoid a short circuit between the gate and the process of forming source and drain regions. 显然这种有氮化硅侧墙结构的自对准MOSFET制造技术,不能满足于短栅长MOSFET制造对低介电常数侧墙结构的要求。 Obviously, this has a self-aligned nitride spacer configuration in MOSFET technology can not meet the short gate length required for manufacturing a MOSFET structure of the low dielectric constant spacers.

[0004] 因此,急需ー种具有低介电常数侧墙结构的自对准MOSFET的制造技木,能够降低栅极与源漏区之间的介电常数,降低栅极与源漏区接触插塞之间的电容,有效提高短栅长MOSFET器件的速度和开关功耗性能。 [0004] Accordingly, an urgent need ー MANUFACTURING TECHNOLOGY wood species having a low dielectric constant self-aligned MOSFET sidewall structure, it is possible to reduce dielectric constant between the gate and the source and drain regions, and source and drain regions to reduce the gate contact plug the capacitance between the plug, effectively improve the short gate length and speed of the switching power MOSFET device performance.

发明内容 SUMMARY

[0005] 本发明的目的在于提供ー种MOSFET制造方法,能够降低栅极与源漏区之间的介电常数,降低栅极与源漏区接触插塞之间的电容,有效提高短栅长MOSFET器件的速度和开关功耗性能 [0005] The object of the present invention to provide a method of manufacturing a MOSFET ー species, the dielectric constant can be reduced between the gate and the source and drain regions, to reduce the gate source and drain regions in contact with the capacitance between the plug, effectively improve the short gate length MOSFET device switching speed and power performance

[0006] 为解决上述问题,本发明提出ー种MOSFET制造方法,该方法包括如下步骤: [0006] In order to solve the above problems, the present invention provides a method of manufacturing a MOSFET ー species, the method comprising the steps of:

[0007] 提供半导体衬底,所述半导体衬底上形成牺牲栅极结构,所述牺牲栅极结构包括栅介质层及其上方的牺牲栅极; [0007] providing a semiconductor substrate, the semiconductor substrate is formed on a sacrificial gate structure, the sacrificial gate structure includes a gate dielectric layer and a sacrificial gate above;

[0008] 在所述半导体衬底和牺牲栅极结构上依次沉积牺牲侧墙层和氮化硅层; [0008] are sequentially deposited on the semiconductor substrate and the sacrificial gate structure and the sacrificial spacer layer, a silicon nitride layer;

[0009] 在所述牺牲栅极结构两侧的半导体衬底中进行离子注入,形成源/漏区; [0009] The ion implantation in the semiconductor substrate on both sides of the sacrificial gate structure, a source / drain region;

[0010] 移除所述氮化硅层,并刻蚀所述牺牲侧墙层形成牺牲侧墙; [0010] removing the silicon nitride layer, and etching the sacrificial sidewall spacer layer forming a sacrificial sidewall spacer;

[0011] 在上述器件结构上方沉积第一层间介质层,并平坦化所述第一层间介质层至暴露出所述牺牲栅极顶部; [0011] depositing a first interlayer dielectric layer above the device structure, and the planarized first interlayer dielectric layer to expose the top of the sacrificial gate;

[0012] 移除所述牺牲栅极得到栅极开孔,在栅极开孔中填充栅极; [0012] removing the sacrificial gate electrode to obtain a gate opening, the gate opening in the gate is filled;

[0013] 在上述器件结构上方采用分子筛エ艺沉积第二层间介质层; [0013] The device structure above said second molecular sieve Ester arts interlayer dielectric layer is deposited;

[0014] 刻蚀所述源/漏区上方的第一层间介质层和第二层间介质层,形成暴露所述源/漏区的自对准接触孔,在所述自对准接触孔中填充接触插塞; [0014] etching the source / drain region of the first interlayer dielectric layer and the second layer above the interlayer dielectric, forming / self-aligned contact hole exposing the source and drain regions, self-aligned contact holes in the filling the contact plugs;

[0015] 等离子体氧化法去除所述牺牲侧墙,形成侧墙空洞; [0015] The plasma oxidation removing the sacrificial sidewall spacer, sidewall cavity is formed;

[0016] 在所述第二层间介质层上沉积第三层间介质层。 [0016] The third interlayer dielectric layer is deposited on the second interlayer dielectric layer.

[0017] 进ー步的,所述牺牲栅极包括多晶硅。 [0017] step into ー, said sacrificial gate includes polysilicon. [0018] 进ー步的,移除所述牺牲栅极采用湿法刻蚀エ艺。 [0018] step into ー, removing the sacrificial gate wet etching Ester arts.

[0019] 进ー步的,所述牺牲侧墙的材料为无定形碳。 [0019] step into ー, the sacrificial sidewall spacer material is amorphous carbon.

[0020] 进ー步的,等离子体氧化法去除所述牺牲侧墙采用的气体为氧气或ニ氧化碳。 [0020] ー step into the plasma oxidation method using the sacrificial spacers gas is oxygen or carbon dioxide ni.

[0021] 进ー步的,所述氮化硅层的沉积厚度为100〜200埃。 [0021] ー step into the silicon nitride layer is deposited to a thickness of 100 ~ 200 Å.

[0022] 进ー步的,移除所述氮化硅层采用干法刻蚀或湿法刻蚀エ艺。 [0022] step into ー, the silicon nitride layer is removed by dry etching or wet etching Ester arts.

[0023] 进ー步的,所述栅极为金属或高K介质材料。 [0023] step into ー, the gate is a metal or a high-K dielectric material.

[0024] 进ー步的,所述沉积第二层间介质层之前还包括对所述栅极进行回刻蚀,以形成栅极回刻开孔,并在所述栅极回刻开孔的侧壁形成补充侧墙。 Before [0024] into ー step, the second interlayer dielectric layer further comprises depositing the gate etched back to form a gate opening etch back, and etching back the gate opening complement sidewall spacer.

[0025] 进ー步的,所述补充侧墙为无定形碳,与所述牺牲侧墙一同被等离子体氧化法去除。 [0025] step into ー, the supplemental sidewall amorphous carbon is removed together with the sacrificial sidewall spacer plasma oxidation.

[0026] 进ー步的,所述接触插塞的材料为金属钨、金属氮化物、氮化钛和氮化铊中的ー种或几种。 [0026] ー step into said contact plug material is tungsten, a metal nitride, titanium nitride, and thallium nitride ー or more species.

[0027] 与现有技术相比,本发明通过等离子体氧化法去除牺牲侧墙以形成侧墙空洞,侧墙空洞的介电常数为1,仅为氮化硅侧墙的七分之一,能显著降低栅极与源漏区接触插塞之间的电容,有效提高短栅长MOSFET器件的速度和开关功耗性能。 [0027] Compared with the prior art, the present invention is by removing the sacrificial sidewall spacer to form a plasma oxidation cavity, the cavity spacer dielectric constant of 1, only one silicon nitride spacers seventh, gate contact can significantly reduce the capacitance between the source and drain regions inserted plug, and improve the speed performance of switching power MOSFET device gate length is short.

附图说明 BRIEF DESCRIPTION

[0028] 图I为本发明实施例的エ艺流程图; [0028] FIG I Ester present invention arts flowchart of one embodiment;

[0029] 图2A至2K为本发明实施例的剖面结构示意图。 [0029] FIGS. 2A to 2K schematic cross-sectional structure of an embodiment of the present invention.

具体实施方式 Detailed ways

[0030] 以下结合附图和具体实施例对本发明提出的MOSFET的制造方法作进ー步详细说明。 [0030] and the specific embodiment of a method of manufacturing a MOSFET proposed by the present invention as further detailed description ー into conjunction with the drawings. 根据下面说明和权利要求书,本发明的优点和特征将更清楚。 The following description and the appended claims, features and advantages of the present invention will be apparent. 需说明的是,附图均采用非常简化的形式,仅用于方便、明晰地辅助说明本发明实施例的目的。 It should be noted that the drawings are used in a very simplified form, for convenience only, assist clarity purpose of illustrating an embodiment of the present invention.

[0031] 如图I所示,本发明提供ー种MOSFET的制造方法,由SI至SlO的十个步骤完成,下面结合图I所示的MOSFET制造エ艺流程图和图2A〜2K所示的M05FET制造エ艺剖面结构示意图对上述MOSFET的制造方法作详细的描述。 [0031] As shown in FIG I, the present invention provides a method of manufacturing a MOSFET ー completed by ten steps SlO to the SI, the following binding 2A~2K I as shown in FIG Ester arts of manufacturing a MOSFET in the flowchart and FIG. Ester M05FET manufacturing arts sectional structural diagram of the method of manufacturing the MOSFET in detail below.

[0032] SI,提供半导体衬底,所述半导体衬底上形成牺牲栅极结构,所述牺牲栅极结构包括栅介质层及其上方的牺牲栅扱。 [0032] SI, a semiconductor substrate, a sacrificial gate structure is formed on the semiconductor substrate, the sacrificial gate structure includes a gate Xi sacrificial gate dielectric layer and above.

[0033] 请參考图2A,提供半导体衬底100,在半导体衬底100上采用化学气相沉积エ艺及刻蚀エ艺形成栅介质层101和牺牲栅极102,所述牺牲栅极102形成于栅介质层101上方,栅介质层101和牺牲栅极102构成牺牲栅极结构,其中,牺牲栅极102在后续的エ艺中将被去除而栅介质层101则始终保留。 [0033] Please refer to FIG. 2A, a semiconductor substrate 100 by chemical vapor deposition and etching Ester Ester Yi Yi forming a gate dielectric layer 101 and sacrificial gate electrode 102 on the semiconductor substrate 100, the sacrificial gate electrode 102 is formed above the gate dielectric layer 101, gate dielectric layer 101 and sacrificial gate electrode 102 constituting the sacrificial gate structure, wherein, the sacrificial gate electrode 102 is removed in the subsequent dielectric layer and the gate arts Ester 101 is always retained. 本实施例中,牺牲栅极102包括多晶硅,栅介质层101可以为氧化硅或氮氧化硅,在65nm技术节点以下,优选高介电常数(高K)材料,如氧化铝,氧化锆,氧化铪等。 In this embodiment, the sacrificial gate electrode 102 comprises polysilicon, gate dielectric layer 101 may be a silicon oxide or silicon oxynitride, in 65nm technology nodes less, preferably a high dielectric constant (high K) materials, such as alumina, zirconia, hafnium.

[0034] S2,在所述半导体衬底和牺牲栅极结构上依次沉积牺牲侧墙层和氮化硅层。 [0034] S2, on the semiconductor substrate and the sacrificial gate structure sequentially depositing a sacrificial layer and a silicon nitride spacer layer.

[0035] 请參考图2B,在所述半导体衬底100和牺牲栅极结构上依次沉积牺牲侧墙层103和氮化硅层104。 [0035] Please refer to Figure 2B, sequentially depositing a sacrificial spacer layer 103 and the silicon nitride layer 104 on the semiconductor substrate 100 and the sacrificial gate structure. 所述牺牲侧墙层103的材料为无定形碳。 The sacrificial sidewall spacer material layer 103 is amorphous carbon. 所述氮化硅层104的沉积厚度为100〜200埃。 Depositing a thickness of the silicon nitride layer 104 is 100 ~ 200 Å. [0036] S3,在所述牺牲栅极结构两侧的半导体衬底中进行离子注入,形成源/漏区。 [0036] S3, ion implantation in the semiconductor substrate on both sides of the sacrificial gate structure, a source / drain region.

[0037] 请參考图2C,以光刻胶(未图示)为掩膜,在所述栅介质层101和牺牲栅极102两侧的半导体衬底中进行离子注入,并对半导体衬底100进行快速退火处理,使注入离子扩散均匀,形成源/漏区105。 [0037] Please refer to 2C, a photoresist (not shown) as a mask, ion implantation in the semiconductor substrate 102 on both sides of the sacrificial gate electrode 101 and the gate dielectric layer, and the semiconductor substrate 100 rapid annealing treatment, a uniform diffusion of the implanted ions to form a source / drain region 105. 本步骤中,氮化硅层104保护牺牲侧墙层103在离子注入后的光刻胶去除时不被剥离。 In this step, the sacrificial protective layer 104 of silicon nitride spacer layer 103 is not peeled off when the resist is removed after the ion implantation.

[0038] S4,移除所述氮化硅层,并刻蚀所述牺牲侧墙层形成牺牲侧墙。 [0038] S4, removing the silicon nitride layer, and etching the sacrificial sidewall spacer is formed sacrificial spacer layer. [0039] 请參考图2D,采用高选择比的干法刻蚀或湿法刻蚀エ艺移除所述氮化硅层104。 [0039] Please refer to Figure 2D, dry etching or wet etching selection ratio higher arts Ester removing the silicon nitride layer 104. 请參考图2E,对牺牲侧墙层103进行刻蚀,形成牺牲侧墙103a。 Referring to FIG 2E, the sacrificial spacer layer 103 is etched to form a sacrificial spacers 103a.

[0040] S5,在上述器件结构上方沉积第一层间介质层,并平坦化至暴露出所述牺牲栅极顶部。 [0040] S5, the above-described device structure is deposited over the first interlayer dielectric layer and planarized to expose the sacrificial gate top.

[0041] 请參考图2F,在半导体衬底100、牺牲侧墙103a和牺牲栅极102上方沉积第一层间介质层106,并化学机械平坦化(CMP)所述第一层间介质层106,直至暴露出所述牺牲栅极102顶部。 [0041] Referring to FIG. 2F, the semiconductor substrate 100, sacrificial spacers 103a and the sacrificial gate electrode 102 is deposited over the first interlayer dielectric layer 106, and chemical mechanical planarization (CMP) of the first interlayer dielectric layer 106 until the top of the sacrificial gate electrode 102 is exposed.

[0042] S6,移除所述牺牲栅极得到栅极开孔,在栅极开孔中填充栅扱。 [0042] S6, removing the sacrificial gate electrode to obtain a gate opening, the gate in the gate opening is filled Xi.

[0043] 请參考图2G,移除所述牺牲栅极102得到栅极开孔,在栅极开孔中填充栅极102a。 [0043] Referring to FIG. 2G, the sacrificial gate electrode 102 is removed to obtain the gate opening, the gate 102a is filled in the gate openings. 移除所述牺牲栅极102采用高选择比的湿法刻蚀エ艺,填充的栅极102a为金属或高K介质材料。 Removing the sacrificial gate electrode 102 using a wet etch to select the gate high ratio Ester arts, 102a is a metal-filled or high-K dielectric material. 本实施例中,在填充完栅极102a之后,还进ー步对所述栅极102a进行回刻蚀,形成栅极回刻开孔(即通过刻蚀去除一部分栅极102a来形成一定深度的开孔),并采用无定形碳在所述栅极回刻开孔的侧壁形成补充侧墙103b,増大后续形成的侧墙空洞尺寸,进ー步减小栅极与源漏区接触插塞之间的电容。 In this embodiment, the gate 102a after completion of the filling, but also into the gate 102a ー further etched back to form a gate opening etch-back (i.e., removing a portion by etching to form a gate electrode 102a of a predetermined depth opening), and using the amorphous carbon etch back gate opening sidewall spacer complement 103b, spacer large void size enlargement of subsequently formed into ー further reduce source and drain regions with the gate contact plug capacitance between.

[0044] S7,在上述器件结构上方采用分子筛エ艺沉积第二层间介质层。 [0044] S7, the above-described device structure over the molecular sieve Ester second interlayer dielectric layer deposition arts.

[0045] 请參考图2H,采用分子筛エ艺沉积第二层间介质层107,这样形成的第二层间介质层107中有许多孔道或空穴,能暴露牺牲侧墙103a和补充侧墙103b顶部,便于后续S8步骤中的气体进入,并氧化去除牺牲侧墙103a和补充侧墙103b。 [0045] Referring to FIG. 2H, depositing a second molecular sieve Ester arts interlayer dielectric layer 107, the second interlayer dielectric layer 107 thus formed has many holes or channels, can expose the sacrificial sidewall spacers 103a and 103b complementary top, facilitating gas into the subsequent step S8, and removing the sacrificial oxide sidewall spacers 103a and supplementary 103b. 进ー步对第二层间介质层107进行CMP,使其表面平坦化并在第一层间介质层106上方保留一定厚度的第二层间介质层107。 The second interlayer dielectric layer further advance ー second interlayer dielectric layer 107. CMP, to planarize the surface and so retain a certain thickness over the first interlayer dielectric layer 106 107.

[0046] S8,刻蚀所述源/漏区上方的第一层间介质层和第二层间介质层,形成暴露源漏区的自对准接触孔,在所述自对准接触孔中填充接触插塞。 [0046] S8, the above etching the source / drain region of the first interlayer dielectric layer and the second interlayer dielectric layer, a self-aligned contact holes exposing source and drain regions of the self-aligned contact hole filling the contact plug.

[0047] 请參考图21,采用自对准接触技术刻蚀所述源/漏区105上方的第一层间介质层106和第二层间介质层107,形成暴露源/漏区的自对准接触孔,在所述自对准接触孔中填充接触插塞108。 A first interlayer dielectric layer 106 and the second interlayer [0047] Please refer to FIG. 21, using the self-aligned contact etching technique source / drain region 105 above the dielectric layer 107 is formed exposing the source / drain regions self- quasi contact hole in the self-aligned contact holes are filled with the contact plug 108. 所述接触插塞108的材料为金属钨、金属氮化物、氮化钛和氮化铊中的一种或几种。 The contact plug material 108 is one or more metals tungsten, a metal nitride, titanium nitride and thallium.

[0048] S9,等离子体氧化法去除所述牺牲侧墙,形成侧墙空洞。 [0048] S9, plasma oxidation removing the sacrificial sidewall spacer, sidewall cavity is formed.

[0049] 请參考图2J,采用等离子体氧化法去除牺牲侧墙103a和补充侧墙103b,形成侧墙空洞103c。 [0049] Referring to FIG. 2J, a plasma oxidation method using sacrificial spacers 103a and supplemental spacer 103b, is formed hollow spacer 103c. 本实施例中,由于牺牲侧墙103a和补充侧墙103b都是无定形碳,所以优选采用氧气或ニ氧化碳气体,通过第二层间介质层107中的的孔道或空穴,对牺牲侧墙103a和补充侧墙103b进行等离子体氧化去除,以形成侧墙空洞103c。 In this embodiment, since the sacrificial sidewall spacers 103a and 103b are added amorphous carbon, it is preferable to use oxygen gas or carbon dioxide gas ni, through bore or hole 107 of the second interlayer dielectric layer, the sacrificial side supplementary wall spacers 103a and 103b is removed plasma oxidation, to form the sidewall cavity 103c. 本方法在完全去除牺牲侧墙103a和补充侧墙103b的同时,不会造成第一层间介质层106,接触插塞108,栅极102a等结构的损伤,提高器件性能,操作简单,节约エ艺成本。 This method, while completely removing the sacrificial sidewall spacers 103a and 103b supplement will not cause the first interlayer dielectric layer 106, damage to the structure of the contact plug 108, a gate 102a, etc., to improve device performance, simple operation, saving Ester Arts and costs. [0050] S10,在所述第二层间介质层上沉积第三层间介质层。 [0050] S10, the third interlayer dielectric layer is deposited on the second interlayer dielectric layer.

[0051] 请參考图2K,在所述第二层间介质层107上沉积第三层间介质层109,以密封保存侧墙空洞,所述第二层间介质层107在此步骤中避免了第三层间介质层109沉积时填入侧墙空洞103c,从而保持了侧墙空洞103c的永久存在,延长器件使用寿命。 [0051] Referring to FIG. 2K, the third interlayer dielectric layer is deposited on the second interlayer dielectric layer 107, 109 to spacer sealed cavity, said second interlayer dielectric layer 107 in this step to avoid the fill the third interlayer dielectric layer 109 is deposited spacer hole 103c, thereby maintaining the permanent presence of spacer hole 103c, to extend the service life of the device.

[0052] 综上所述,本发明通过等离子体氧化法去除牺牲侧墙以形成侧墙空洞,侧墙空洞的介电常数为1,仅为氮化硅侧墙的七分之一,能显著降低栅极与源漏区接触插塞之间的电容,有效提高短栅长MOSFET器件的速度和开关功耗性能;本发明提供的制造方法エ艺简单,节约成本,形成的侧墙空洞能够永久存在,能延长器件的使用寿命。 [0052] In summary, the present invention is removed by a plasma oxidation process to form the sacrificial sidewall spacer cavity, the cavity spacer dielectric constant of 1, only one silicon nitride spacers seventh, significantly source and drain regions and reduce gate capacitance between the contact plug is inserted, effectively improve the short gate length of the MOSFET device switching speed and power performance; the present invention provides a method for producing Ester simple process, cost savings, can be permanently formed in the cavity sidewalls present, can extend the lifetime of the device.

[0053] 显然,本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。 [0053] Obviously, those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. 这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。 Thus, if these modifications and variations of the present invention fall within the claims of the invention and the scope of equivalents thereof, the present invention intends to include these modifications and variations.

Claims (11)

1. ー种MOSFET制造方法,其特征在于,包括: 提供半导体衬底,所述半导体衬底上形成牺牲栅极结构,所述牺牲栅极结构包括栅介质层及其上方的牺牲栅极; 在所述半导体衬底和牺牲栅极结构上依次沉积牺牲侧墙层和氮化硅层; 在所述牺牲栅极结构两侧的半导体衬底中进行离子注入,形成源/漏区; 移除所述氮化硅层,并刻蚀所述牺牲侧墙层形成牺牲侧墙; 在上述器件结构上方沉积第一层间介质层,并平坦化所述第一层间介质层至暴露出所述牺牲栅极顶部; 移除所述牺牲栅极得到栅极开孔,在栅极开孔中填充栅极; 在上述器件结构上方采用分子筛エ艺沉积第二层间介质层; 刻蚀所述源/漏区上方的第一层间介质层和第二层间介质层,形成暴露所述源/漏区的自对准接触孔,在所述自对准接触孔中填充接触插塞; 等离子体氧化法去除所述牺牲侧墙, 1. A method of manufacturing MOSFET ー species, characterized by comprising: providing a semiconductor substrate, a sacrificial gate structure is formed on the semiconductor substrate, the sacrificial gate structure includes a gate dielectric layer and over the sacrificial gate; in the sequentially deposited on the semiconductor substrate and the sacrificial gate structure and the sacrificial spacer layer, silicon nitride layer; ion implantation in the semiconductor substrate on both sides of the sacrificial gate structure, a source / drain region; removing the said silicon nitride layer, and etching the sacrificial sidewall spacer is formed the sacrificial spacer layer; depositing a first interlayer dielectric layer above the device structure, and the planarized first interlayer dielectric layer to expose the sacrificial top gate; removing the sacrificial gate electrode to obtain a gate opening, the gate opening in the gate is filled; with a second interlayer dielectric layer deposited over a molecular sieve Ester arts above device structure; etching the source / above the drain region of the first interlayer dielectric layer and the second interlayer dielectric layer, which exposes the source / drain regions self-aligned contact hole in the self-aligned contact holes are filled with contact plugs; plasma oxidation removing the sacrificial sidewall spacer method, 成侧墙空洞; 在所述第二层间介质层上沉积第三层间介质层。 Into the spacer cavity; depositing a third interlayer dielectric layer on said second interlayer dielectric layer.
2.如权利要求I所述的MOSFET制造方法,其特征在于,所述牺牲栅极包括多晶硅。 The method of manufacturing a MOSFET according to I as claimed in claim 2, wherein said sacrificial gate includes polysilicon.
3.如权利要求I所述的MOSFET制造方法,其特征在于,移除所述牺牲栅极采用湿法刻蚀エ艺。 The method of manufacturing a MOSFET according to I as claimed in claim 3, wherein removing the sacrificial gate wet etching Ester arts.
4.如权利要求I所述的MOSFET制造方法,其特征在于,所述牺牲侧墙的材料为无定形碳。 4. The method of manufacturing a MOSFET according to claim I, wherein the sacrificial spacer material is amorphous carbon.
5.如权利要求4所述的MOSFET制造方法,其特征在于,等离子体氧化法去除所述牺牲侧墙采用的气体为氧气或ニ氧化碳。 5. The method of manufacturing a MOSFET according to claim 4, wherein the gas plasma oxidation removing the sacrificial sidewall spacer used is oxygen or carbon dioxide ni.
6.如权利要求I所述的MOSFET制造方法,其特征在于,所述氮化硅层的沉积厚度为100 〜200 埃。 The method of manufacturing a MOSFET according to I as claimed in claim 6, wherein the silicon nitride layer is deposited to a thickness of 100 ~ 200 Å.
7.如权利要求I所述的MOSFET制造方法,其特征在于,移除所述氮化硅层采用干法刻蚀或湿法刻蚀エ艺。 7. The method of manufacturing a MOSFET according to claim I, wherein the silicon nitride layer is removed by dry etching or wet etching Ester arts.
8.如权利要求I所述的MOSFET制造方法,其特征在于,所述栅极为金属或高K介质材料。 8. A method of manufacturing a MOSFET according to claim I, wherein said gate electrode is a metal or a high-K dielectric material.
9.如权利要求I所述的MOSFET制造方法,其特征在于,所述沉积第二层间介质层之前还包括对所述栅极进行回刻蚀,以形成栅极回刻开孔,并在所述栅极回刻开孔的侧壁形成补充侧墙。 9. The method of manufacturing a MOSFET according to claim I, wherein said depositing further comprises the gate is etched back until the second interlayer dielectric layer, an etch-back to form a gate opening, and the back gate sidewall spacer complement engraved opening.
10.如权利要求9所述的MOSFET制造方法,其特征在于,所述补充侧墙为无定形碳,与所述牺牲侧墙一同被等离子体氧化法去除。 10. The method of manufacturing a MOSFET according to claim 9, wherein said supplemental spacer amorphous carbon is removed together with the sacrificial sidewall spacer plasma oxidation.
11.如权利要求I所述的MOSFET制造方法,其特征在于,所述接触插塞的材料为金属钨、金属氮化物、氮化钛和氮化铊中的ー种或几种。 11. The method of manufacturing a MOSFET according to claim I, wherein said contact plug material is one or more metal ー tungsten, a metal nitride, titanium nitride and thallium.
CN201110039626.XA 2011-02-17 2011-02-17 Manufacturing method of MOSFET (metal-oxide-semiconductor field effect transistor) CN102646589B (en)

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