CN102779852B - SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure - Google Patents
SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure Download PDFInfo
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- CN102779852B CN102779852B CN201210248535.1A CN201210248535A CN102779852B CN 102779852 B CN102779852 B CN 102779852B CN 201210248535 A CN201210248535 A CN 201210248535A CN 102779852 B CN102779852 B CN 102779852B
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Abstract
The invention discloses a SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with a composite gate dielectric structure, and belongs to the technical field of power semiconductor devices. A thought of differentiating modulation of electric fields is adopted according to difference of intensities of electric fields and difference of defect concentrations of gate dielectrics in different areas, namely, high-k gate dielectrics are adopted in channel regions with high-defect concentration and a low electric field, so that a large quantity of trap states caused by using a SiO2/SiC interface is avoided; the influence on Fowler-Nordheim (FN) tunneling current is obviously reduced; and meanwhile, because the electric field intensity in a channel injection area is small, the reduction on gate dielectric breakdown voltage caused by small offset of conduction band/valence band is weakened; and moreover, a SiO2 gate dielectric (a junction field-effect transistor (JFET) area is formed in a way of extension and is not subjected to ion injection, the surface quality of the JFET area is good, and the SiO2/SiC interface state is low) is adopted by the JFET area with low defect concentration and a high electric field, and enough high conduction band offset is supplied by the SiO2 dielectric, so that the ahead breakdown of the gate dielectric is avoided.
Description
Technical field
The invention belongs to power semiconductor technical field, relate to double-diffusion metal-oxide-semiconductor field effect transistor (DMOS) device architecture, especially a kind of carborundum (SiC) DMOS device with gate stack structure.
Background technology
Carborundum (SiC) is as a kind of semiconductor material with wide forbidden band receiving much concern in recent years, owing to thering is the excellent physical characteristics such as broad stopband, high critical breakdown electric field, high heat conductance, high electronics saturation drift velocity, thereby have broad application prospects in high temperature, high-power, high frequency, strong irradiation field.
Compare with semiconductor material with wide forbidden band such as gallium nitride (GaN), SiC material can directly generate silicon dioxide (SiO by thermal oxidation
2), this advantage makes SiC become the ideal material of making high-power MOSFET device.As shown in Figure 1, device gate medium is SiO to conventional SiC DMOS device architecture
2.But due to SiC/SiO
2there are a large amount of traps in interface, thereby causes the low channel mobility of SiC DMOS device and serious gate medium integrity problem.For this problem, at present the most frequently used method is at nitric oxide (NO) or nitrous oxide (N in the world
2o) in atmosphere, carry out the char residue that gate oxidation or the method for annealing remove interface, thereby reduce interface trap, improve device inversion-layer channel mobility and gate medium reliability.But this method, when reducing interfacial state, has increased fixed charge, thereby has caused the drift of SiC DMOS device threshold voltage.On the other hand, due to SiC and SiO
2the difference of dielectric constant, according to Gauss law, the electric field strength in oxide is approximately 3 times in SiC.It has been generally acknowledged that the critical breakdown electric field that SiC material approaches oxide layer place is 2MV/cm, therefore the electric field strength in oxide layer is up to 6MV/cm, thereby cause that semi-conducting material and grid metal inject electronics to gate medium, produce Fowler-Nordheim(FN) tunnelling current, while causing medium, become and puncture (time-dependent dielectric breakdown, TDDB), make SiCDMOS device face very serious gate medium integrity problem.And for Si MOSFET device, because the critical breakdown electric field of Si material itself is than the low magnitude of SiC material, so the electric field strength in gate medium is little, gate medium integrity problem is also not obvious.
Because the electric field strength in gate medium and dielectric constant are inversely proportional to, and the FN tunnelling current that affects gate medium reliability is directly proportional to the electric field strength in medium, therefore adopts the dielectric material of high-k (high-k) to replace the gate medium SiO of current use
2thereby, reduce the electric field strength in dielectric layer, suppress FN tunnelling current, improve the reliability of gate medium.High-k gate medium SiC DMOS device architecture as shown in Figure 2.But because dielectric breakdown electric field, conduction band/valence band offset amount of high-k gate medium compares SiO
2little, use separately high-k gate medium can reduce the puncture voltage of gate medium.Therefore foreign study person proposes the SiC DMOS device of multi-layer gate dielectric structure, as shown in Figure 3.First at SiC surface heat growth one deck SiO
2, subsequently at SiO
2deposit one deck high-k gate medium on layer.This multi-layer gate dielectric structure passes through SiO on the one hand
2medium provides sufficiently high conduction band offset amount, reduces FN tunnelling current on the other hand by high-k medium.But because the defect of surface ion after injecting is many, therefore at the SiO in Channeling implantation district
2still there are a large amount of trap states in/SiC interface, this has not only reduced channel mobility, simultaneously a large amount of SiC/SiO
2interface trap forms FN tunnelling current together with inducing trap with High-Field, the gate dielectric breakdown that this grid structure can only partial rcsponse FN tunnelling current causes.
Summary of the invention
The object of the present invention is to provide a kind of SiC VDMOS device with gate stack structure, this device can effectively reduce the FN tunnelling current of device, improves the long-term reliability of gate medium.
Core concept of the present invention is: in traditional Si C VDMOS device architecture, introduce gate stack structure, main according to the difference of the electric field strength of zones of different under gate dielectric layer and defect concentration, adopt the thought of subregion Electric Field Modulated, defect concentration larger low electric field region use high-k gate medium, at high electric field region, use SiO
2gate medium, thus the electric field strength in gate medium reduced, reduce FN tunnelling current, improve the reliability of gate medium.
Technical scheme of the present invention is as follows:
A SiC VDMOS device with gate stack structure, its structure cell as shown in Figure 4, comprising: metal gate electrode 1, polysilicon gate 2, gate medium, source metal electrode 5, silicon carbide N
+source region 6, carborundum P
+contact zone 7, carborundum P-base district 8, silicon carbide N
–drift region 9, silicon carbide N
+substrate 10, the metal leakage utmost point 11; Cellular is the metal leakage utmost point 11, silicon carbide N from the bottom up successively
+substrate 10, silicon carbide N
–drift region 9; In silicon carbide N-drift region, 9 both sides, top have respectively a carborundum P-base district 8, have silicon carbide N separate but that contact with each other in each carborundum P-base district 8
+source region 6 and carborundum P
+contact zone 7; Unit's cellular surface both sides are and silicon carbide N
+source region 6 and carborundum P
+the source metal electrode 5 that contact zone 7 all contacts, in the middle of first cellular surface is and silicon carbide N
+the gate medium that source region 6, carborundum P-base district 8 all contact with silicon carbide N-drift region 9; Gate medium surface is polysilicon gate 2, and polysilicon gate 2 surfaces are metal gate electrodes 1.Described gate medium is gate stack structure, by high-k (high-k) gate medium 3 and SiO
2gate medium 4 is composited.SiO wherein
2gate medium 4 is covered in two silicon carbide Ns between carborundum P-base district 8
–9 surfaces, drift region, i.e. surface, the JFET district of device; And high-dielectric-coefficient grid medium 3 is covered in the surface in two carborundum P-base districts 8, the channel region of device is surperficial.The dielectric constant of described high-dielectric-coefficient grid medium 3 is higher than SiO
2dielectric constant.
Operation principle of the present invention:
The SiC VDMOS device with gate stack structure provided by the invention, according to the difference of the difference of the electric field strength of zones of different under gate medium and defect concentration, adopt the thought of subregion Electric Field Modulated: the channel region at high defect concentration, low electric field adopts high-k gate medium, thereby has avoided employing SiO
2a large amount of trap states that/SiC interface causes, have significantly reduced the impact of FN tunnelling current, simultaneously because the electric field strength in Channeling implantation district is less, have therefore weakened the reduction of the smaller gate dielectric breakdown voltage causing of conduction band/valence band offset amount; And adopt SiO in the JFET district of fabricating low-defect-density, high electric field
2(JFET region is formed by extension gate medium, does not carry out Implantation, and surface quality is good, SiO
2/ SiC interfacial state is lower), SiO
2medium can provide sufficiently high conduction band offset amount, thereby has avoided puncturing in advance of gate medium.
Accompanying drawing explanation
Fig. 1 is traditional SiC VDMOS device architecture schematic diagram.
Fig. 2 is high-k gate medium SiC VDMOS device architecture schematic diagram.
Fig. 3 is multi-layer gate medium SiC VDMOS device architecture schematic diagram.
Fig. 4 is a kind of gate stack SiC VDMOS device architecture schematic diagram provided by the invention.
Fig. 5 is the schematic diagram of a kind of expansion structure of a kind of gate stack SiC VDMOS device architecture provided by the invention.
In Fig. 1 to Fig. 5: the 1st, metal gate electrode, the 2nd, polysilicon gate, the 3rd, high-k (high-k) gate medium, the 4th, SiO
2gate medium, the 5th, source metal electrode, the 6th, silicon carbide N
+source region, the 7th, carborundum P
+contact zone, the 8th, carborundum P-base district, the 9th, silicon carbide N
-drift region, the 10th, silicon carbide N
+substrate, the 11st, the metal leakage utmost point.
Embodiment
For technical scheme and superiority of the present invention that the present invention will be explained are clearer, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Embodiment described herein only, for explaining the present invention, is not intended to limit the present invention.
A SiC VDMOS device with gate stack structure, its structure cell as shown in Figure 4, comprising: metal gate electrode 1, polysilicon gate 2, gate medium, source metal electrode 5, silicon carbide N
+source region 6, carborundum P
+contact zone 7, carborundum P-base district 8, silicon carbide N-drift region 9, silicon carbide N
+substrate 10, the metal leakage utmost point 11; Cellular is the metal leakage utmost point 11, silicon carbide N from the bottom up successively
+substrate 10, silicon carbide N
–drift region 9; In silicon carbide N-drift region, 9 both sides, top have respectively a carborundum P-base district 8, have silicon carbide N separate but that contact with each other in each carborundum P-base district 8
+source region 6 and carborundum P
+contact zone 7; Unit's cellular surface both sides are and silicon carbide N
+source region 6 and carborundum P
+the source metal electrode 5 that contact zone 7 all contacts, in the middle of first cellular surface is and silicon carbide N
+source region 6, carborundum P-base district 8 and silicon carbide N
–the gate medium that drift region 9 all contacts; Gate medium surface is polysilicon gate 2, and polysilicon gate 2 surfaces are metal gate electrodes 1.Described gate medium is gate stack structure, by high-k (high-k) gate medium 3 and SiO
2gate medium 4 is composited.SiO wherein
2gate medium 4 is covered in two silicon carbide Ns between carborundum P-base district 8
–9 surfaces, drift region, i.e. surface, the JFET district of device; And high-dielectric-coefficient grid medium 3 is covered in the surface in two carborundum P-base districts 8, the channel region of device is surperficial.The dielectric constant of described high-dielectric-coefficient grid medium 3 is higher than SiO
2dielectric constant.
In technique scheme, described gate stack structure can have different execution modes.Such as:
One, the silicon carbide N between two carborundum P-base districts 8 first
-9 surfaces, drift region (being the surface, JFET district of device) deposition SiO
2gate medium 4, then at the surface in two carborundum P-base districts 8 (being the surface, channel region of device) deposition high-dielectric-coefficient grid medium 3.
Two, first 9 surfaces, silicon carbide N-drift region between two carborundum P-base districts 8 (being the surface, JFET district of device) deposits SiO
2gate medium 4, then at the surface in two carborundum P-base districts 8 (being the surface, channel region of device) and SiO
2gate medium 4 surface deposition high-dielectric-coefficient grid medium 3(as shown in Figure 5).
Three, (being the surface, channel region of device) deposition high-dielectric-coefficient grid medium 3, then silicon carbide N between two carborundum P-base districts 8 first on the surface in two carborundum P-base districts 8
–9 surfaces, drift region (being the surface, JFET district of device) and high-dielectric-coefficient grid medium 3 surface deposition SiO
2gate medium 4.
Above three kinds of modes all can realize described gate stack structure, and the effect of SiC VDMOS device is not had to obvious difference.
Claims (5)
1. a SiC VDMOS device with gate stack structure, its structure cell comprises: metal gate electrode (1), polysilicon gate (2), gate medium, source metal electrode (5), silicon carbide N
+source region (6), carborundum P
+contact zone (7), carborundum P-base district (8), carborundum N – drift region (9), silicon carbide N
+substrate (10), the metal leakage utmost point (11); Cellular is the metal leakage utmost point (11), silicon carbide N from the bottom up successively
+substrate (10), carborundum N – drift region (9); In both sides, top, carborundum N – drift region (9), there is respectively a carborundum P-base district (8), in each carborundum P-base district (8), there is silicon carbide N separate but that contact with each other
+source region (6) and carborundum P
+contact zone (7); Unit's cellular surface both sides are and silicon carbide N
+source region (6) and carborundum P
+the source metal electrode (5) that contact zone (7) all contacts, in the middle of first cellular surface is and silicon carbide N
+the gate medium that source region (6), carborundum P-base district (8) and carborundum N – drift region (9) all contact; Gate medium surface is polysilicon gate (2), and polysilicon gate (2) surface is metal gate electrode (1);
It is characterized in that, described gate medium is gate stack structure, by high-dielectric-coefficient grid medium (3) and SiO
2gate medium (4) is composited; SiO wherein
2gate medium (4) is covered in the surface, carborundum N – drift region (9) between two carborundum P-base districts (8), i.e. surface, the JFET district of device; And high-dielectric-coefficient grid medium (3) is covered in the surface in two carborundum P-base districts (8), the channel region of device is surperficial; The dielectric constant of described high-dielectric-coefficient grid medium (3) is higher than SiO
2dielectric constant.
2. the SiC VDMOS device with gate stack structure according to claim 1, is characterized in that, described high-dielectric-coefficient grid medium (3) material is HfO
2, Si
3n
4, TiO
2, Al
2o
3or ZrO
2.
3. the SiC VDMOS device with gate stack structure according to claim 1 and 2, it is characterized in that, the implementation of described gate stack structure is: the first surface, carborundum N – drift region (9) between two carborundum P-base districts (8), i.e. the JFET district surface deposition SiO of device
2gate medium (4), then on the surface in two carborundum P-base districts (8), i.e. the channel region surface deposition high-dielectric-coefficient grid medium (3) of device.
4. the SiC VDMOS device with gate stack structure according to claim 1 and 2, it is characterized in that, the implementation of described gate stack structure is: the first surface, carborundum N – drift region (9) between two carborundum P-base districts (8), i.e. the JFET district surface deposition SiO of device
2gate medium (4), then on the surface in two carborundum P-base districts (8), i.e. surface, channel region and the SiO of device
2gate medium (4) surface deposition high-dielectric-coefficient grid medium (3).
5. the SiC VDMOS device with gate stack structure according to claim 1 and 2, it is characterized in that, the implementation of described gate stack structure is: first on the surface in two carborundum P-base districts (8), it is the channel region surface deposition high-dielectric-coefficient grid medium (3) of device, then the surface, carborundum N – drift region (9) between two carborundum P-base districts (8), the i.e. surface, JFET district of device and high-dielectric-coefficient grid medium (3) surface deposition SiO
2gate medium (4).
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| CN102779852B true CN102779852B (en) | 2014-09-10 |
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