GB2205993A - Method of manufacturing a trench capacitor - Google Patents

Method of manufacturing a trench capacitor Download PDF

Info

Publication number
GB2205993A
GB2205993A GB08808824A GB8808824A GB2205993A GB 2205993 A GB2205993 A GB 2205993A GB 08808824 A GB08808824 A GB 08808824A GB 8808824 A GB8808824 A GB 8808824A GB 2205993 A GB2205993 A GB 2205993A
Authority
GB
United Kingdom
Prior art keywords
trench
layer
capacitor
external surface
selecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GB08808824A
Other versions
GB8808824D0 (en
Inventor
Ju-Ho Song
Dae-Hee Hahn
Geung-Won Kang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Semiconductor and Telecomunications Co Ltd
Original Assignee
Samsung Semiconductor and Telecomunications Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Semiconductor and Telecomunications Co Ltd filed Critical Samsung Semiconductor and Telecomunications Co Ltd
Publication of GB8808824D0 publication Critical patent/GB8808824D0/en
Publication of GB2205993A publication Critical patent/GB2205993A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Description

1 2205993 METHOD OF MANUFACTURING A TRENCH CAPACITOR The present invention
relates to a method of manufacturing trench capacitors, particularly of the type suitable for use in high capacity memory cell arrays. The invention also relates to a capacitor formed by the method.
Much development has been undertaken in order to increase memory capacity by increasing the density of memory cells. For this purpose, it is important to reduce the area of individual memory cells since the overall area of a semiconductor chip is limited. Generally, individual memory cells consist of a single transistor and a single capacitor. With this arrangement, the capacitor occupies most of the area of the cell. resulting in limitation of the integration scale of, for example a Megabit DRAM. This is a result of the fact that the capacitance should be large enough to ensure reliability against the S/N ratio of the Read Signal and soft error. In order to solve these problems. the trench capacitor, which can enlarge the effective area of a capacitor while reducing the surface area thereof. is used in the formation of memory cells, for example in Megabit DRAM deviced. The conventional fabrication method for formation of a trench capacitor 2 is as follows. First, an oxide pattern is defined on the silicon substrate for use as a mask during Reactive Ion Etching (RIE) of the trench. After the silicon substrate is etched using the Reactive Ion Etching process, a capacitor oxide is grown on the walls of the trench. The trench is subsequently filled with polysilicon using a conventional UCVD (Low Pressure Chemical Vapor Deposition) method. Next etchback of the polysilicon is undertaken to achieve planarization. Finally. the polysilicon electrode pattern is formed.
Figure 1 illustrates an ideal MOS trench capacitor, which exhibits no undercut in the trench profile. In practice, however, an undercut is caused by the additional processing steps which are necessary to achieve rounding off of the trench edges.
When the trench capacitor is fabricated using conventional techniques the trench is formed with an undercut as shown in Figure 2A. As a result, voids are generated in the trench. because of the polysilicon deposition kinematics involved in the LPCV1) process. During the etch-back process, the void defects of the trench are revealed (Figure 2B). As a result chemical etchants become trapped in the voids and this causes problems during subsequent processing ste.ps.
Therefore, the principal object of this invention is to provide a trench capacitor fabrication method which does not produce voids in the trench during polysilicon 3 deposition, in spite of the presence of an undercut trench profile.
According to the present invention there is provided a method of manufacturing a trench capacitor comprising the steps of:- forming a trench in a substrate; producing a capacitor oxide on the walls of the trench; producing a first layer of material over the capacitor oxide; shaping the external surface of the said first layer so as to ensure that the said external surface does not present an undercut profile; and producing a second layer of material over the said first layer so as to fill the trench.
Embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings. in which.--- Figure 1 illustrates a vertical section through an ideal trench capacitor without any undercut; Figures 2(A)-(B) illustrate vertical sections through a conventional trench capacitor at.respective fabrication stages, the trench having an undercut; Figures 3(A)-(E) are vertical sections illustrating a fabrication process in accordance with an embodiment of the present invention.
4 Referring to Figures 3(A)-(E), a method of fabrication of a trench capacitor in accordance with the present invention is illustrated.
Figure 3(A) illustrates the initial formation of trench 12, by Reactive Ion Etching of a silicon substrate 10. That is, an oxide 11 is grown on silicon substrate 10 and the oxide is coated with a photoresist. Subsequently, the trench pattern is defined on the silicon substrate 10, by conventional photolithography. The trench 12 is then formed by Reactive Ion Etching. Specifically, the RIE may be conducted using 5-25 SCCM (Standard Cubic Centimeter) of BC1 3r 30-55 SCCM of Cl 2 10-30 mTorr of pressure, and -200 to -300 V of DC voltage.
Figure 3(B) shows deposition of the first polysilicon layer 14 over the walls of the trench subsequent to the growth of a capacitor oxide 13. The capacitor oxide 13 is 100-250 h (1 - 2.5 x 10- 8 m) thick and is thermally grown. The first polysilicon layer 14, which has a thickness of 0.3 - 0.4 times the width of the mouth of the trench, is deposited using the LPCV1) method. During this process, a trench shaped recess 15, mirroring the undercut shape of the trench 12 itself, is formed because the polysilicon is deposited uniformly over the walls of trench 12.
W Figure 3(C) illustrates a further processing stage in which recess 15 is reshaped by etch-back of the first polysilicon layer 14, so as to form a trench shaped recess 16. Specifically. after deposition of the -first polysilicon layer 14, the polysilicon is etched back to a thickness of 0.2 - 0.3 times the width of the mouth of the trench 12. The following etching. conditions may be used: 45 - 60 SCCM of He, 170 - 180 SCCM of SF 6r 800 - 950 mTorr of pressure. 45 - 55 watt of power. The resulting trench shaped recess 16 does not mirror the undercut of the original trench.
Figure 3(D) illustrates deposition of a second polysilicon layer 17, into the trench shaped recess 16. Polysilicon layer 17 has a thickness of 0.6 0.8 times the width of the mouth of the trench 12 and is deposited using the LPWD method. Layer 17 completely fills recess 16.
Figure 3(E) illustrates formation of a third polysilicon layer (the final electrode 18) over the trench. Planarization of the surface is achieved by etch-back of the second polysilicon layer 17 under the same etching conditions as mentioned above for etch-back of the first polysilicon layer 14. The electrode pattern is formed by deposition of the third polysilicon layer 18 using the LPWD method.
6 From the above description. it will be appreciated that the void defects conventionally resulting from the undercut profile of the trench are avoided. This is achieved by shaping of a first polysilicon layer and filling of the resultant trench shaped recess by a second polysilicon layer.
Various modifications can be made without departing from the scope of the invention and such modifications will be readily apparent to those skilled in the art. For example, the method is not necessarily restricted to use with silicon substrates and polysilicon layers.
11 0 7

Claims (16)

Claims: -
1. A method of manufacturing a trench capacitor comprising the steps of:forming a trench in a substrate;producing a capacitor oxide on the walls of the trench; producing a first layer of material over the capacitor oxide; shaping the external surface of the said first layer so as to ensure that the said external surface does not present an undercut profile; and producing a second layer of material over the said first layer so as to fill the trench.
2. A method as claimed in claim 1, wherein the step of shaping the said external surface comprises etch-back of the first layer of material.
3. A method as claimed in claim 1 or claim 2, wherein the step of forming the trench comprises the formation of an oxide mask on the substrate and Reactive Ion Etching using the mask.
1
4. A method as claimed in any preceding claim, wherein the production of the first and second layers is achieved by Low Pressure Chemical Vapour Deposition.
8
5. A method as claimed in any preceding claim, comprising the step of producing a third layer of material over the second layer of material.
6. A method as claimed in claim 5, comprising the step of shaping the external surface of the second layer of material prior to production of the said third-layer.
7. A method as claimed in claim 6, wherein the step of shaping the external surface of the said second layer comprises etch-back of the second layer.
8. A method as claimed in any preceding claim, comprising the step of selecting the substrate to be formed of silicon and selecting the material of the first and second layers to be polysilicon.
9. A method as claimed in claim 3, wherein the Reactive Ion Etching is carried out in accordance with the following conditions: 5 - 25 SCCM of BC1 30 30 - 55 SCCM of CL 2' 10 - 30 mTorr of pressure, and -200 to -300 V of DC bias voltage.
10. A method as claimed in any preceding claim, comprising the step of selecting the initial thickness of the said first layer to be 0.3 - 0.4 times the width of the mouth of the trench.
h 1 9
11. A method as claimed in any preceding claim, comprising the step of selecting the thickness of the re-shaped first layer at the mouth of the trench to be 0.2 0.3 times the width of the mouth of the trench.
12. A method as claimed in any preceding claim, comprising the step of selecting the initial thickness of the said second layer to be 0.6 - 0.8 times the width of the mouth of the trench.
13. A method as claimed in claim 2, wherein the etch-back is carried out in accordance with the following conditions: 45 - 60 S= of He, 170 SWM of SF 6# 800 - 950 mTorr of pressure, and 45 -55 watt of power.
14. A method as claimed in claim 7, wherein the etch-back of the said second layer is carried out in accordance with the conditions specified in claim 13.
15. A method of manufacturing a trench capacitor, substantially as hereinbefore described with reference to and as illustrated in Figures 3(A)-(E) of the accompanying drawings.
16. A trench capacitor manufactured in accordance with any preceding claim.
Published 1988 at The Patent Office. State House. 66 71 High Holborn. London WC1P. 4TP. Further erpies maybe obtained from The Patent Office, Sales Branch, St Mary Cray, Orpington. Kent BR5 3RD. Printed by Multiplex teckiniques ltd. St Mary Cray. Kent. Con. 1187. Sales Branch, St Mary Cray, Orpington. Kent BR5 3RD. Printed by Multiplex teckiniques ltd. St Mary Cray. Kent. Con. 1187.
GB08808824A 1987-04-30 1988-04-14 Method of manufacturing a trench capacitor Pending GB2205993A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870004242A KR900003262B1 (en) 1987-04-30 1987-04-30 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
GB8808824D0 GB8808824D0 (en) 1988-05-18
GB2205993A true GB2205993A (en) 1988-12-21

Family

ID=19261098

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08808824A Pending GB2205993A (en) 1987-04-30 1988-04-14 Method of manufacturing a trench capacitor

Country Status (6)

Country Link
JP (1) JPS63299263A (en)
KR (1) KR900003262B1 (en)
DE (1) DE3812621A1 (en)
FR (1) FR2614731B1 (en)
GB (1) GB2205993A (en)
NL (1) NL8801030A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0145606A2 (en) * 1983-12-13 1985-06-19 Fujitsu Limited Semiconductor memory device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5681968A (en) * 1979-12-07 1981-07-04 Toshiba Corp Manufacture of semiconductor device
DE3045922A1 (en) * 1980-12-05 1982-07-08 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING STRUCTURES OF LAYERS CONSTRUCTED FROM SILICIDES OR FROM SILICIDE-POLYSILIZIUM BY REACTIVE SPUTTERING
US4450042A (en) * 1982-07-06 1984-05-22 Texas Instruments Incorporated Plasma etch chemistry for anisotropic etching of silicon
DE3315719A1 (en) * 1983-04-29 1984-10-31 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING STRUCTURES FROM METAL SILICIDES OR SILICIDE-POLYSILIZIUM EXISTING DOUBLE LAYERS FOR INTEGRATED SEMICONDUCTOR CIRCUITS THROUGH REACTIVE ION NETWORK
JPS6079737A (en) * 1983-10-05 1985-05-07 Nec Corp Manufacture of semiconductor device
JPS61288460A (en) * 1985-06-17 1986-12-18 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory device and manufacture thereof
US4714520A (en) * 1985-07-25 1987-12-22 Advanced Micro Devices, Inc. Method for filling a trench in an integrated circuit structure without producing voids
US4801988A (en) * 1986-10-31 1989-01-31 International Business Machines Corporation Semiconductor trench capacitor cell with merged isolation and node trench construction

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0145606A2 (en) * 1983-12-13 1985-06-19 Fujitsu Limited Semiconductor memory device

Also Published As

Publication number Publication date
KR880013247A (en) 1988-11-30
JPH0520908B2 (en) 1993-03-22
NL8801030A (en) 1988-11-16
FR2614731A1 (en) 1988-11-04
GB8808824D0 (en) 1988-05-18
DE3812621A1 (en) 1988-11-17
KR900003262B1 (en) 1990-05-12
JPS63299263A (en) 1988-12-06
FR2614731B1 (en) 1992-01-03

Similar Documents

Publication Publication Date Title
USRE37505E1 (en) Stacked capacitor construction
US6077754A (en) Methods of forming a silicon nitride film, a capacitor dielectric layer and a capacitor
JP3501297B2 (en) Method for manufacturing semiconductor memory device
JP2519612B2 (en) Method for producing silicon layer with maximized surface area
US7432152B2 (en) Methods of forming HSG layers and devices
JPH0629465A (en) Capacitor and its manufacture
KR950012554B1 (en) Method of manufacturing a storage node of vlsi semiconductor device
JPH05217815A (en) Manufacture and structure of memory cell capacitor
JP3222944B2 (en) Method for manufacturing capacitor of DRAM cell
US5956595A (en) Method of fabricating a semiconductor integrated circuit having a capacitor with lower electrode comprising titanium nitride
US5683938A (en) Method for filling contact holes with metal by two-step deposition
US6103568A (en) Manufacturing method of cylindrical stacked electrode
US5972771A (en) Enhancing semiconductor structure surface area using HSG and etching
US5441908A (en) Capacitor of a semiconductor device having increased effective area
US5346846A (en) Method of manufacturing a highly integrated semiconductor device
JP2622243B2 (en) Method of manufacturing stack capacitor for semiconductor device
GB2205993A (en) Method of manufacturing a trench capacitor
KR950006982B1 (en) Charge storaging node manufacturing method
JPH065805A (en) Manufacture of semiconductor device
US6232240B1 (en) Method for fabricating a capacitor
JP2882387B2 (en) Method for manufacturing semiconductor device
KR20000025636A (en) Method for manufacturing capacitor of semiconductor memory device
KR100712489B1 (en) Semiconductor memory device and method for manufacturing the same
US6133085A (en) Method for making a DRAM capacitor using a rotated photolithography mask
JPH0363828B2 (en)

Legal Events

Date Code Title Description
732 Registration of transactions, instruments or events in the register (sect. 32/1977)