USRE37505E1 - Stacked capacitor construction - Google Patents

Stacked capacitor construction Download PDF

Info

Publication number
USRE37505E1
USRE37505E1 US08/628,287 US62828796A USRE37505E US RE37505 E1 USRE37505 E1 US RE37505E1 US 62828796 A US62828796 A US 62828796A US RE37505 E USRE37505 E US RE37505E
Authority
US
United States
Prior art keywords
electrically conductive
storage node
doped polysilicon
stacked capacitor
striations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/628,287
Inventor
Guy Blalock
Phillip G. Wald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to US08/628,287 priority Critical patent/USRE37505E1/en
Application granted granted Critical
Publication of USRE37505E1 publication Critical patent/USRE37505E1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/964—Roughened surface

Definitions

  • This invention relates generally to three dimensional sack capacitors and the fabrication thereof.
  • a principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three dimensional cell capacitors such as trenched or stacked capacitors. This invention concerns stacked capacitor cell constructions.
  • the capacitor With the conventional stacked capacitor, the capacitor is formed immediately above and electrically connected to the active device area of the associated MOS transistor of the memory cell. Typically, only the upper surface of the lower storage polysilicon node of the capacitor is utilized for capacitance.
  • some attempts have been made to provide constructions to increase capacitance, whereby the back side of one capacitor terminal is used to store charge. Such is shown by way of example by T. Ema et al. “3-Dimensional Stacked Capacitor Cell For 16M and 64M DRAMS”, IEDM Tech. Digest, pp. 592, 595, 1988 and S. Inoue et al., “A Spread Stacked Capacitor (SSC) Cell For 64 MBit DRAMs”, IEDM Tech. Digest, pp. 31-34, 1989.
  • SSC Spread Stacked Capacitor
  • FIG. 1 illustrates a semiconductor wafer fragment 10 comprised of a bulk substrate 12 , word lines 14 , 16 , field oxide region 18 , and an active area 20 for connection with a capacitor.
  • Wafer 10 also comprises a layer of insulating dielectric 22 through which a desired contact opening 24 has been provided to active area 20 .
  • contact opening 24 has an elliptical or circular shape with walls 26 .
  • FIG. 1 illustrate shading only for identifying sidewalls 26 and depicting a smooth surface which arcs into the page. Such lines do not indicate texture or other patterning. Sidewalls 26 are typically smooth and straight.
  • the elliptical shape of contact 24 can be produced by depositing a photoresist film over the bulk substrate 10 and transferring the contact 24 pattern by photolithographic means using the proper image mask.
  • a layer 28 of conductive material such as conductively doped polysilicon, is deposited atop wafer 10 and to within contact opening 24 .
  • Layer 28 will provide the storage node poly for formation of one of the capacitor plates.
  • polysilicon layer 28 is first chemical mechanical polished or resist planerization dry etched to be flush with the upper surface of insulating layer 22 . Thereafter, insulating layer 22 is etched selectively relative to polysilicon to produce an isolated storage node 30 having the illustrated crown portions projecting upwardly from layer 22 . Thereafter, a cell dielectric would be deposited, followed by a cell polysilicon layer to complete the capacitor construction.
  • FIG. 1 is a cross sectional/elevational view of a semiconductor wafer fragment processed in accordance with prior art techniques, and is described in the “Background” section above.
  • FIG. 2 is a top view of the FIG. 1 wafer fragment, with the line 1 — 1 illustrating where the FIG. 1 section cut is taken.
  • FIG. 3 is a cross section/elevational view of the FIG. 1 wafer fragment illustrated at a processing step subsequent to that shown by FIGS. 1 and 2.
  • FIG. 4 is a cross sectional/elevational view of the FIG. 1 wafer fragment illustrated at a processing step subsequent to that shown by FIG. 3 .
  • FIG. 5 is a cross sectional/elevational view of a semiconductor wafer fragment processed in accordance with the invention.
  • FIG. 6 is a top view of the FIG. 5 wafer fragment, with the line 5 — 5 illustrating where the FIG. 5 section cut is taken.
  • FIG. 7 is a cross sectional/elevational view of the FIG. 5 wafer fragment illustrated at a processing step subsequent to that shown by FIGS. 5 and 6.
  • FIG. 8 is a top view of the FIG. 7 wafer fragment, with the line 7 — 7 illustrating where the FIG. 7 section cut is taken.
  • FIG. 9 is a cross sectional/elevational view of the FIG. 5 wafer fragment illustrated at a processing step subsequent to that shown by FIGS. 7 and 8.
  • FIG. 10 is a cross sectional/elevational view of the FIG. 9 wafer fragment taken through line 10 — 10 in FIG. 9 .
  • FIG. 11 is a cross sectional/elevational view of the FIG. 5 wafer fragment illustrated at a processing step subsequent to that shown by FIGS. 9 and 10.
  • FIG. 12 is a cross sectional/elevational view of the FIG. 11 wafer fragment taken through line 12 — 12 in FIG. 11 .
  • FIG. 13 is a cross sectional/elevational view of the FIG. 5 wafer illustrated at a processing step subsequent to that shown by FIG. 12 .
  • FIG. 14 is a top view of a prior art capacitor contact opening.
  • FIG. 15 is a top view of a capacitor contact opening produced in accordance with the invention.
  • a method of forming a capacitor on a semiconductor wafer comprises the following steps:
  • the electrically conductive material filling the grooved striations of the capacitor contact opening thereby defining striated external conductive material sidewalls within the capacitor contact opening which are male complementary its shape to the female capacitor contact opening striations;
  • a stacked capacitor construction formed within a semiconductor substrate comprises:
  • an electrically conductive storage node having upwardly rising external sidewalls, the upwardly rising external sidewalls having longitudinally extending striations to maximize surface area and corresponding capacitance;
  • a striated cell dielectric layer provided over the storage node and its associated longitudinally extending striations
  • an electrically conductive striated cell layer provided over the striated cell dielectric layer.
  • FIG. 5 illustrates a semiconductor wafer fragment 40 comprised of a bulk silicon substrate 42 , word lines 44 , 46 , field oxide region 48 , and active area 50 .
  • a layer 52 of insulating dielectric, such as SiO 2 is also provided to a selected thickness.
  • a unique capacitor contact opening 54 is etched through insulating layer 52 to upwardly expose contact opening 54 .
  • contact opening 54 results from a selective anisotropic dry etch in a dry etching reactor to produce a minimum selected open dimension “A” into insulating dielectric layer 52 .
  • a wider open dimension “C” for contact opening 54 results from the elliptical shape.
  • Such etching is conducted utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component.
  • the flow rate of the bombarding component significantly and effectively exceeds the flow rate of the reactive component to produce capacitor contact opening 54 having grooved striated sidewalls 56 .
  • striated sidewalls have peak ridges 55 and low valleys 57 , which define (for purposes of continuing discussion) female capacitor contact opening striations 58 .
  • Effective excess flow of an inert gas bombarding component, as compared to the reactive gas component has been determined to enable controllable production of the illustrated striations.
  • the bombarding gas component is preferably selected from the group consisting of argon, krypton and xenon or mixtures thereof.
  • the invention was reduced to practice utilizing argon.
  • the reactive gas component need be reactive with the insulating material of layer 52 . Where such layer comprises SiO 2 , reactive gas components of CF 4 and CHF 3 would be operable.
  • the flow rate to the reactor of the bombarding gas component is sufficient to produce a partial pressure of bombarding gas within the reactor of greater than or equal to about 31 mTorr.
  • Argon, CF 4 and CF 3 are known prior art components for etching smooth-walled contact openings through SiO 2 layers but not utilized in the manner claimed in this document
  • a conventional prior art process for etching a prior art contact opening 24 (FIG. 1) into a SiO 2 layer of dielectric in an Applied Materials P5000TM etcher includes argon at 50 sccm, CF 4 at 20 sccm, and CHF 3 at 25 sccm, providing a total reactor pressure of 100 mTorr. Such provides a partial pressure of argon within the reactor of approximately 50 mTorr, with such an etch producing substantially smooth contact opening sidewalls.
  • This invention was reduced to practice, in part, utilizing the same Applied Materials P5000TM reactor and flow rates of Ar at 90 sccm, CF 4 at 20 sccm, and CHF 3 at 25 sccm.
  • Total reactor pressure was 50 mTorr
  • power supplied was 700
  • magnetic field strength was 75 gauss
  • oxide thickness was 2 microns
  • the runs were conducted for 300 seconds.
  • the P5000TM etcher has an internal volume of 4.6 liters, which produced a partial pressure of Ar at a 90 sccm flow rate of 31 mTorr.
  • Example runs were also conducted at Ar flow rates of 60 sccm and 110 sccm, with the flow rates of CF 4 and CHF 3 for each such run being maintained at 20 sccm and 25 sccm, respectively.
  • the 60 sccm Ar flow rate example produced no striations
  • the 110 sccm Ar flow rate produced significant striations equal or greater in magnitude than that produced by the 90 sccm example above. From such data, it is apparent that the desired striations can be produced where the flow rate of the bombarding gas component significantly exceeds the flow rate of the reactive component in an amount sufficient to effectively produce grooved striated contact opening sidewalls and thereby define female capacitor contact opening striations.
  • a layer 60 of electrically conductive material such as conductively doped polysilicon, is provided atop wafer 10 and within striated capacitor contact opening 54 to a selected thickness “B” which is less than the selected open dimension “A”. Electrically conductive material 60 fills grooved striations 58 of capacitor contact opening 54 . This thereby defines a striated external conductive material sidewall 62 within capacitor contact opening 54 which has external male striations 59 which are complementary in shape to female capacitor contact opening striations 58 . Selected thickness “B” is most preferably less than or equal to about 30% of minimum selected open contact dimension “A” to provide sufficient space within contact opening 54 for subsequent provision of a capacitor dielectric layer and cell polysilicon layer.
  • An example preferred thickness for poly layer 60 would be 1200 Angstroms. Such could be deposited by known techniques, and thereafter further texturized as desired. As illustrated, striations from external conductive material sidewall 62 transfer to an internal conductive material sidewall 65 , producing internal male striations 59 a
  • thickness “B” of polysilicon layer 60 is removed atop dielectric 52 by a conventional polish or etching technique to define an isolated capacitor storage node within insulating dielectric layer 52 .
  • Insulating dielectric layer 52 is then selectively etched relative to polysilicon layer 60 to expose at least a portion of external male striated conductive material sidewalls 62 and associated external male striations 59 (FIG. 10 ).
  • a conformal capacitor dielectric layer 64 such as Si 3 N 4 , is conformally deposited atop the etched conductive material 60 and over its exposed striated sidewalls 62 .
  • Such striations translate through capacitor dielectric layer 64 such that its external surface 67 is as well striated.
  • internal conductive material striations 59 a translate to striate internal capacitor dielectric material sidewalls 69 .
  • a conformal capacitor cell layer 66 of conductive material such as conductively doped polysilicon, is conformally deposited atop capacitor dielectric layer 64 . Striations from internal and external surfaces of layer 64 will probably only partially translate to outer surfaces of layer 66 due to the increasing thickness and corresponding smoothing effect imparted by subsequent layers. Layers 66 and 64 may be subsequently etched, as desired, to pattern desired capacitor constructions.
  • FIGS. 14 and 15 show a prior art contact 100
  • FIG. 15 shows a contact 200 in accordance with the invention, both of which are made from the same photo tool.
  • Contact 100 has some effective or average radius “r”
  • contact 200 has an effective or average radius “r”, which is slightly greater than “r”, thus increasing surface area.
  • the intent is to maximize flow of the bombarding component, while minimizing total reactor pressure, and thereby increase the flow rate of argon relative to the reactive gas components.
  • the invention functions by providing a pretexturized, striated surface before polysilicon is deposited to maximize surface area in both external and internal portions of the deposited polysilicon. The resultant product is improved over the prior art the result of increased capacitance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations; b) providing a layer of an electrically conductive storage node material within the striated capacitor contact opening; c) removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric having striated sidewalls; d) etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of the external male striated conductive material sidewalls; and e) providing conformal layers of capacitor dielectric and capacitor cell material atop the etched conductive material and over its exposed striated sidewalls. The invention also includes a stacked capacitor construction having an electrically conductive storage node with upwardly rising external sidewalls. Such sidewalls have longitudinally extending striations to maximize surface area and corresponding capacitance in a resulting construction.

Description

RELATED PATENT DATA
This patent resulted from a divisional application of U.S. patent application Ser. No. 07/854,435, filed Mar. 18, 1992, which is now U.S. Pat. No. 5,238,862.
TECHNICAL FIELD
This invention relates generally to three dimensional sack capacitors and the fabrication thereof.
BACKGROUND OF THE INVENTION
As DRAMs increase in memory cell density, there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area A principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three dimensional cell capacitors such as trenched or stacked capacitors. This invention concerns stacked capacitor cell constructions.
With the conventional stacked capacitor, the capacitor is formed immediately above and electrically connected to the active device area of the associated MOS transistor of the memory cell. Typically, only the upper surface of the lower storage polysilicon node of the capacitor is utilized for capacitance. However, some attempts have been made to provide constructions to increase capacitance, whereby the back side of one capacitor terminal is used to store charge. Such is shown by way of example by T. Ema et al. “3-Dimensional Stacked Capacitor Cell For 16M and 64M DRAMS”, IEDM Tech. Digest, pp. 592, 595, 1988 and S. Inoue et al., “A Spread Stacked Capacitor (SSC) Cell For 64 MBit DRAMs”, IEDM Tech. Digest, pp. 31-34, 1989.
One standard prior art technique for forming a stacked “crown” cell capacitor is described with reference to FIGS. 1-4. “Crown” capacitors are characterized by upward spire-like, or fin-like projections, thereby increasing surface area and corresponding capacitance as compared to planar capacitors. FIG. 1 illustrates a semiconductor wafer fragment 10 comprised of a bulk substrate 12, word lines 14, 16, field oxide region 18, and an active area 20 for connection with a capacitor. Wafer 10 also comprises a layer of insulating dielectric 22 through which a desired contact opening 24 has been provided to active area 20. Referring to FIGS. 1 and 2, contact opening 24 has an elliptical or circular shape with walls 26. The vertical lines illustrated in FIG. 1 illustrate shading only for identifying sidewalls 26 and depicting a smooth surface which arcs into the page. Such lines do not indicate texture or other patterning. Sidewalls 26 are typically smooth and straight. The elliptical shape of contact 24 can be produced by depositing a photoresist film over the bulk substrate 10 and transferring the contact 24 pattern by photolithographic means using the proper image mask.
Referring to FIG. 3, a layer 28 of conductive material, such as conductively doped polysilicon, is deposited atop wafer 10 and to within contact opening 24. Layer 28 will provide the storage node poly for formation of one of the capacitor plates.
Referring to FIG. 4, polysilicon layer 28 is first chemical mechanical polished or resist planerization dry etched to be flush with the upper surface of insulating layer 22. Thereafter, insulating layer 22 is etched selectively relative to polysilicon to produce an isolated storage node 30 having the illustrated crown portions projecting upwardly from layer 22. Thereafter, a cell dielectric would be deposited, followed by a cell polysilicon layer to complete the capacitor construction.
It is an object of this invention to enable such and similar stacked capacitor constructions to have increased capacitance.
BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
FIG. 1 is a cross sectional/elevational view of a semiconductor wafer fragment processed in accordance with prior art techniques, and is described in the “Background” section above.
FIG. 2 is a top view of the FIG. 1 wafer fragment, with the line 1—1 illustrating where the FIG. 1 section cut is taken.
FIG. 3 is a cross section/elevational view of the FIG. 1 wafer fragment illustrated at a processing step subsequent to that shown by FIGS. 1 and 2.
FIG. 4 is a cross sectional/elevational view of the FIG. 1 wafer fragment illustrated at a processing step subsequent to that shown by FIG. 3.
FIG. 5 is a cross sectional/elevational view of a semiconductor wafer fragment processed in accordance with the invention.
FIG. 6 is a top view of the FIG. 5 wafer fragment, with the line 5—5 illustrating where the FIG. 5 section cut is taken.
FIG. 7 is a cross sectional/elevational view of the FIG. 5 wafer fragment illustrated at a processing step subsequent to that shown by FIGS. 5 and 6.
FIG. 8 is a top view of the FIG. 7 wafer fragment, with the line 7—7 illustrating where the FIG. 7 section cut is taken.
FIG. 9 is a cross sectional/elevational view of the FIG. 5 wafer fragment illustrated at a processing step subsequent to that shown by FIGS. 7 and 8.
FIG. 10 is a cross sectional/elevational view of the FIG. 9 wafer fragment taken through line 10—10 in FIG. 9.
FIG. 11 is a cross sectional/elevational view of the FIG. 5 wafer fragment illustrated at a processing step subsequent to that shown by FIGS. 9 and 10.
FIG. 12 is a cross sectional/elevational view of the FIG. 11 wafer fragment taken through line 12—12 in FIG. 11.
FIG. 13 is a cross sectional/elevational view of the FIG. 5 wafer illustrated at a processing step subsequent to that shown by FIG. 12.
FIG. 14 is a top view of a prior art capacitor contact opening.
FIG. 15 is a top view of a capacitor contact opening produced in accordance with the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
In accordance with one aspect of the invention, a method of forming a capacitor on a semiconductor wafer comprises the following steps:
providing a layer of insulating dielectric atop a semiconductor wafer to a selected thickness;
in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into the insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations;
providing a layer of electrically conductive material atop the wafer and within the striated capacitor contact opening to a selected thickness which is less than the selected open dimension, the electrically conductive material filling the grooved striations of the capacitor contact opening thereby defining striated external conductive material sidewalls within the capacitor contact opening which are male complementary its shape to the female capacitor contact opening striations;
removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric;
etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of the external male striated conductive material sidewalls;
providing a conformal capacitor dielectric layer atop the etched conductive material and over its exposed striated sidewalls; and
providing a conformal capacitor cell layer of electrically conductive material atop the capacitor dielectric layer.
In accordance with another aspect of the invention, a stacked capacitor construction formed within a semiconductor substrate comprises:
an electrically conductive storage node, the storage node having upwardly rising external sidewalls, the upwardly rising external sidewalls having longitudinally extending striations to maximize surface area and corresponding capacitance;
a striated cell dielectric layer provided over the storage node and its associated longitudinally extending striations; and
an electrically conductive striated cell layer provided over the striated cell dielectric layer.
More particularly and with reference to the figures, FIG. 5 illustrates a semiconductor wafer fragment 40 comprised of a bulk silicon substrate 42, word lines 44, 46, field oxide region 48, and active area 50. A layer 52 of insulating dielectric, such as SiO2, is also provided to a selected thickness. A unique capacitor contact opening 54 is etched through insulating layer 52 to upwardly expose contact opening 54.
More specifically, contact opening 54 results from a selective anisotropic dry etch in a dry etching reactor to produce a minimum selected open dimension “A” into insulating dielectric layer 52. A wider open dimension “C” for contact opening 54 results from the elliptical shape. Such etching is conducted utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component. The flow rate of the bombarding component significantly and effectively exceeds the flow rate of the reactive component to produce capacitor contact opening 54 having grooved striated sidewalls 56. As illustrated, striated sidewalls have peak ridges 55 and low valleys 57, which define (for purposes of continuing discussion) female capacitor contact opening striations 58. Effective excess flow of an inert gas bombarding component, as compared to the reactive gas component, has been determined to enable controllable production of the illustrated striations.
The bombarding gas component is preferably selected from the group consisting of argon, krypton and xenon or mixtures thereof. The invention was reduced to practice utilizing argon. The reactive gas component need be reactive with the insulating material of layer 52. Where such layer comprises SiO2, reactive gas components of CF4 and CHF3 would be operable. Preferably, the flow rate to the reactor of the bombarding gas component is sufficient to produce a partial pressure of bombarding gas within the reactor of greater than or equal to about 31 mTorr.
Argon, CF4and CF3 are known prior art components for etching smooth-walled contact openings through SiO2 layers but not utilized in the manner claimed in this document For example, a conventional prior art process for etching a prior art contact opening 24 (FIG. 1) into a SiO2 layer of dielectric in an Applied Materials P5000™ etcher includes argon at 50 sccm, CF4 at 20 sccm, and CHF3 at 25 sccm, providing a total reactor pressure of 100 mTorr. Such provides a partial pressure of argon within the reactor of approximately 50 mTorr, with such an etch producing substantially smooth contact opening sidewalls. This invention was reduced to practice, in part, utilizing the same Applied Materials P5000™ reactor and flow rates of Ar at 90 sccm, CF4 at 20 sccm, and CHF3 at 25 sccm. Total reactor pressure was 50 mTorr, power supplied was 700, magnetic field strength was 75 gauss, oxide thickness was 2 microns, and the runs were conducted for 300 seconds. The P5000™ etcher has an internal volume of 4.6 liters, which produced a partial pressure of Ar at a 90 sccm flow rate of 31 mTorr. Example runs were also conducted at Ar flow rates of 60 sccm and 110 sccm, with the flow rates of CF4 and CHF3 for each such run being maintained at 20 sccm and 25 sccm, respectively. The 60 sccm Ar flow rate example produced no striations, while the 110 sccm Ar flow rate produced significant striations equal or greater in magnitude than that produced by the 90 sccm example above. From such data, it is apparent that the desired striations can be produced where the flow rate of the bombarding gas component significantly exceeds the flow rate of the reactive component in an amount sufficient to effectively produce grooved striated contact opening sidewalls and thereby define female capacitor contact opening striations.
Referring to FIGS. 7 and 8, a layer 60 of electrically conductive material such as conductively doped polysilicon, is provided atop wafer 10 and within striated capacitor contact opening 54 to a selected thickness “B” which is less than the selected open dimension “A”. Electrically conductive material 60 fills grooved striations 58 of capacitor contact opening 54. This thereby defines a striated external conductive material sidewall 62 within capacitor contact opening 54 which has external male striations 59 which are complementary in shape to female capacitor contact opening striations 58. Selected thickness “B” is most preferably less than or equal to about 30% of minimum selected open contact dimension “A” to provide sufficient space within contact opening 54 for subsequent provision of a capacitor dielectric layer and cell polysilicon layer. An example preferred thickness for poly layer 60 would be 1200 Angstroms. Such could be deposited by known techniques, and thereafter further texturized as desired. As illustrated, striations from external conductive material sidewall 62 transfer to an internal conductive material sidewall 65, producing internal male striations 59a
Referring to FIGS. 9 and 10, thickness “B” of polysilicon layer 60 is removed atop dielectric 52 by a conventional polish or etching technique to define an isolated capacitor storage node within insulating dielectric layer 52. Insulating dielectric layer 52 is then selectively etched relative to polysilicon layer 60 to expose at least a portion of external male striated conductive material sidewalls 62 and associated external male striations 59 (FIG. 10).
Referring to FIGS. 11 and 12, a conformal capacitor dielectric layer 64 such as Si3N4, is conformally deposited atop the etched conductive material 60 and over its exposed striated sidewalls 62. Such striations translate through capacitor dielectric layer 64 such that its external surface 67 is as well striated. Additionally, internal conductive material striations 59a translate to striate internal capacitor dielectric material sidewalls 69.
Referring to FIG. 13, a conformal capacitor cell layer 66 of conductive material, such as conductively doped polysilicon, is conformally deposited atop capacitor dielectric layer 64. Striations from internal and external surfaces of layer 64 will probably only partially translate to outer surfaces of layer 66 due to the increasing thickness and corresponding smoothing effect imparted by subsequent layers. Layers 66 and 64 may be subsequently etched, as desired, to pattern desired capacitor constructions.
The above-described technique and construction increases contact sidewall surface area significantly over the prior art for maximization of capacitance for a given photo feature size. The prior art embodiment of FIGS. 1-4 and the embodiment of the invention of FIGS. 5-13 utilize the same photo tool. Yet, a greater surface area of the contact opening is produced as a result of the described anisotropic dry etch which effectively increases the radius of the inventive contact over that of the standard prior art contact. The effect is shown in contrast in FIGS. 14 and 15. FIG. 14 shows a prior art contact 100, while FIG. 15 shows a contact 200 in accordance with the invention, both of which are made from the same photo tool. Contact 100 has some effective or average radius “r”, while contact 200 has an effective or average radius “r”, which is slightly greater than “r”, thus increasing surface area.
The intent is to maximize flow of the bombarding component, while minimizing total reactor pressure, and thereby increase the flow rate of argon relative to the reactive gas components. The invention functions by providing a pretexturized, striated surface before polysilicon is deposited to maximize surface area in both external and internal portions of the deposited polysilicon. The resultant product is improved over the prior art the result of increased capacitance.
In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims (83)

We claim:
1. A stacked capacitor construction formed within a semiconductor substrate comprising:
an electrically conductive storage node, the storage node having upwardly rising external sidewalls, the upwardly rising external sidewalls having longitudinally extending striations to maximize surface area and corresponding capacitance;
a striated cell dielectric layer provided over the storage node and its associated longitudinally extending striations; and
an electrically conductive striated cell layer provided over the striated cell dielectric layer.
2. The stacked capacitor construction of claim 1 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
3. The stacked capacitor construction of claim 1 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
4. The stacked capacitor construction of claim 1 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
5. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a striated sidewall;
an electrically conductive storage node formed within the at least one contact opening the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive cell layer provided over the cell dielectric layer, the electrically conductive cell layer including striations.
6. The stacked capacitor construction of claim 5 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
7. The stacked capacitor construction of claim 5 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
8. The stacked capacitor construction of claim 5 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
9. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a striated sidewall;
an electrically conductive storage node formed within the at least one contact opening, the storage node having rising external sidewalls, the rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the rising external sidewalls including striations;
a dielectric layer provided over the storage node and its associated rising external sidewalls, the dielectric layer including striations; and
an electrically conductive cell layer provided over the cell dielectric layer, the electrically conductive cell layer including striations.
10. The stacked capacitor construction of claim 9 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
11. The stacked capacitor construction of claim 9 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
12. The stacked capacitor construction of claim 9 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
13. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a striated sidewall;
an electrically conductive storage node, the storage node having upwardly rising external sidewalls, the upwardly rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated upwardly rising sidewalls, the cell dielectric layer including striations; and
an electrically conductive cell layer provided over the cell dielectric layer, the electrically conductive cell layer including striations.
14. The stacked capacitor construction of claim 13 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
15. The stacked capacitor construction of claim 13 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
16. The stacked capacitor construction of claim 13 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
17. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a pretexturized striated sidewall;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striated sidewalls;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
18. The stacked capacitor construction of claim 17 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
19. The stacked capacitor construction of claim 17 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
20. The stacked capacitor construction of claim 17 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
21. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a pretexturized striated sidewall;
an electrically conductive storage node, the storage node having rising external sidewalls, the rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated rising external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
22. The stacked capacitor construction of claim 21 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
23. The stacked capacitor construction of claim 21 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
24. The stacked capacitor construction of claim 21 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
25. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a pretexturized striated sidewall;
an electrically conductive storage node, the storage node having upwardly rising external sidewalls, the upwardly rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated upwardly rising external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
26. The stacked capacitor construction of claim 25 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
27. The stacked capacitor construction of claim 25 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
28. The stacked capacitor construction of claim 25 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
29. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a grooved striated sidewall;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
30. The stacked capacitor construction of claim 29 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
31. The stacked capacitor construction of claim 29 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
32. The stacked capacitor construction of claim 29 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
33. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a grooved striated sidewall;
an electrically conductive storage node, the storage node having rising external sidewalls, the rising external sidewalls each having a surface thereon including to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated rising external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
34. The stacked capacitor construction of claim 33 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
35. The stacked capacitor construction of claim 33 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
36. The stacked capacitor construction of claim 33 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
37. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a grooved striated sidewall;
an electrically conductive storage node, the storage node having upwardly rising external sidewalls, the upwardly rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the upwardly rising external sidewalls including striations;
a dielectric layer provided over the storage node and its associated upwardly rising sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
38. The stacked capacitor construction of claim 37 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
39. The stacked capacitor construction of claim 37 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
40. The stacked capacitor construction of claim 37 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
41. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including complementary striations therein to the striations in the sidewall of the at least one contact opening of the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its associated external sidewalls; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
42. The stacked capacitor construction of claim 41 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
43. The stacked capacitor construction of claim 41 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
44. The stacked capacitor construction of claim 41 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
45. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having rising external sidewalls, the rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the rising external sidewalls including complementary striations therein to the striations in the sidewall of the at least one contact opening of the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its associated rising external surfaces, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
46. The stacked capacitor construction of claim 45 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
47. The stacked capacitor construction of claim 45 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
48. The stacked capacitor construction of claim 45 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
49. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having upwardly rising external sidewalls, the upwardly rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the upwardly rising external sidewalls including complementary striations therein to the striations in the sidewall of the at least one contact opening of the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its associated upwardly rising external surfaces, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
50. The stacked capacitor construction of claim 49 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
51. The stacked capacitor construction of claim 49 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
52. The stacked capacitor construction of claim 49 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
53. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external side walls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
54. The stacked capacitor construction of claim 53 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
55. The stacked capacitor construction of claim 53 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
56. The stacked capacitor construction of claim 53 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
57. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having raised external sidewalls, the raised external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the raised external sidewalls including striations;
a dielectric layer provided over the storage node and its associated raised external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
58. The stacked capacitor construction of claim 57 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
59. The stacked capacitor construction of claim 57 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
60. The stacked capacitor construction of claim 57 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
61. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having upwardly raised external sidewalls, the upwardly raised external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the upwardly raised external sidewalls including striations;
a dielectric layer provided over the storage node and its associated upwardly raising external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
62. The stacked capacitor construction of claim 61 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
63. The stacked capacitor construction of claim 61 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
64. The stacked capacitor construction of claim 61 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
65. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein;
an electrically conductive storage node formed within the at least one contact opening, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive cell layer provided over the cell dielectric layer, the electrically conductive cell layer including striations.
66. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a texturized surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external side walls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
67. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external side walls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, a portion of the surface of the electrically conductive layer including partial striations.
68. A stacked capacitor construction formed within a semiconductor substrate comprising:
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
69. The stacked capacitor construction of claim 68 wherein the electrically conductive storage node comprises conductively doped polysilicon.
70. The stacked capacitor construction of claim 68 wherein the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
71. The stacked capacitor construction of claim 68 wherein the electrically conductive storage node comprises conductively doped polysilicon and the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
72. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a minimum selected open contact dimension;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations, the electrically conductive storage node having a thickness, the thickness less than about 30 % of the minimum selected open contact dimension of the contact opening in the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
73. The stacked capacitor construction of claim 72 wherein the electrically conductive storage node comprises conductively doped polysilicon.
74. The stacked capacitor construction of claim 72 wherein the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
75. The stacked capacitor construction of claim 72 wherein the electrically conductive storage node comprises conductively doped polysilicon and the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
76. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a minimum selected open contact dimension;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations the electrically conductive storage node having a thickness, the thickness less equal to about 30 % of the minimum selected open contact dimension of the contact opening in the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
77. The stacked capacitor construction of claim 76 wherein the electrically conductive storage node comprises conductively doped polysilicon.
78. The stacked capacitor construction of claim 76 wherein the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
79. The stacked capacitor construction of claim 76 wherein the electrically conductive storage node comprises conductively doped polysilicon and the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
80. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a selected open contact dimension;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations, the electrically conductive storage node having a thickness, the thickness less than the minimum selected open contact dimension of the contact opening in the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
81. The stacked capacitor construction of claim 80 wherein the electrically conductive storage node comprises conductively doped polysilicon.
82. The stacked capacitor construction of claim 80 wherein the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
83. The stacked capacitor construction of claim 80 wherein the electrically conductive storage node comprises conductively doped polysilicon and the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
US08/628,287 1992-03-18 1996-04-05 Stacked capacitor construction Expired - Lifetime USRE37505E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/628,287 USRE37505E1 (en) 1992-03-18 1996-04-05 Stacked capacitor construction

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/854,435 US5238862A (en) 1992-03-18 1992-03-18 Method of forming a stacked capacitor with striated electrode
US08/058,778 US5300801A (en) 1992-03-18 1993-04-28 Stacked capacitor construction
US08/628,287 USRE37505E1 (en) 1992-03-18 1996-04-05 Stacked capacitor construction

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/058,778 Reissue US5300801A (en) 1992-03-18 1993-04-28 Stacked capacitor construction

Publications (1)

Publication Number Publication Date
USRE37505E1 true USRE37505E1 (en) 2002-01-15

Family

ID=25318683

Family Applications (3)

Application Number Title Priority Date Filing Date
US07/854,435 Expired - Lifetime US5238862A (en) 1992-03-18 1992-03-18 Method of forming a stacked capacitor with striated electrode
US08/058,778 Ceased US5300801A (en) 1992-03-18 1993-04-28 Stacked capacitor construction
US08/628,287 Expired - Lifetime USRE37505E1 (en) 1992-03-18 1996-04-05 Stacked capacitor construction

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US07/854,435 Expired - Lifetime US5238862A (en) 1992-03-18 1992-03-18 Method of forming a stacked capacitor with striated electrode
US08/058,778 Ceased US5300801A (en) 1992-03-18 1993-04-28 Stacked capacitor construction

Country Status (1)

Country Link
US (3) US5238862A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020060335A1 (en) * 1997-06-24 2002-05-23 Todd Edgar Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same
US20030045069A1 (en) * 2001-08-30 2003-03-06 Brent Gilgen Capacitor for use in an integrated circuit
US20030089940A1 (en) * 2001-04-19 2003-05-15 Micron Technology, Inc. Integrated circuit memory with offset capacitor

Families Citing this family (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677428A (en) * 1992-08-25 1994-03-18 Nec Corp Semiconductor memory and manufacture thereof
US5498562A (en) 1993-04-07 1996-03-12 Micron Technology, Inc. Semiconductor processing methods of forming stacked capacitors
US5494841A (en) * 1993-10-15 1996-02-27 Micron Semiconductor, Inc. Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells
GB2285176B (en) * 1993-12-27 1997-11-26 Hyundai Electronics Ind Structure and manufacturing method of a charge storage electrode
US5691219A (en) * 1994-09-17 1997-11-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor memory device
US5438011A (en) * 1995-03-03 1995-08-01 Micron Technology, Inc. Method of forming a capacitor using a photoresist contact sidewall having standing wave ripples
US5838620A (en) 1995-04-05 1998-11-17 Micron Technology, Inc. Circuit for cancelling and replacing redundant elements
US5967030A (en) 1995-11-17 1999-10-19 Micron Technology, Inc. Global planarization method and apparatus
US5812468A (en) * 1995-11-28 1998-09-22 Micron Technology, Inc. Programmable device for redundant element cancel in a memory
US5763911A (en) * 1996-06-05 1998-06-09 Pacesetter, Inc. Micro-cellular capacitor for use in implantable medical devices
US6190992B1 (en) 1996-07-15 2001-02-20 Micron Technology, Inc. Method to achieve rough silicon surface on both sides of container for enhanced capacitance/area electrodes
US5912579A (en) * 1997-02-06 1999-06-15 Zagar; Paul S. Circuit for cancelling and replacing redundant elements
US5994166A (en) * 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
US6331488B1 (en) 1997-05-23 2001-12-18 Micron Technology, Inc. Planarization process for semiconductor substrates
US6316363B1 (en) 1999-09-02 2001-11-13 Micron Technology, Inc. Deadhesion method and mechanism for wafer processing
US6055611A (en) * 1997-07-09 2000-04-25 Micron Technology, Inc. Method and apparatus for enabling redundant memory
US6043119A (en) * 1997-08-04 2000-03-28 Micron Technology, Inc. Method of making a capacitor
US6384446B2 (en) * 1998-02-17 2002-05-07 Agere Systems Guardian Corp. Grooved capacitor structure for integrated circuits
US6228775B1 (en) 1998-02-24 2001-05-08 Micron Technology, Inc. Plasma etching method using low ionization potential gas
JPH11251540A (en) * 1998-02-26 1999-09-17 Oki Electric Ind Co Ltd Semiconductor device and its manufacture
US6174817B1 (en) 1998-08-26 2001-01-16 Texas Instruments Incorporated Two step oxide removal for memory cells
US6218316B1 (en) 1998-10-22 2001-04-17 Micron Technology, Inc. Planarization of non-planar surfaces in device fabrication
US6358793B1 (en) * 1999-02-26 2002-03-19 Micron Technology, Inc. Method for localized masking for semiconductor structure development
US6303956B1 (en) * 1999-02-26 2001-10-16 Micron Technology, Inc. Conductive container structures having a dielectric cap
US6518172B1 (en) 2000-08-29 2003-02-11 Micron Technology, Inc. Method for applying uniform pressurized film across wafer
US6639266B1 (en) 2000-08-30 2003-10-28 Micron Technology, Inc. Modifying material removal selectivity in semiconductor structure development
US6346455B1 (en) 2000-08-31 2002-02-12 Micron Technology, Inc. Method to form a corrugated structure for enhanced capacitance
US6498088B1 (en) 2000-11-09 2002-12-24 Micron Technology, Inc. Stacked local interconnect structure and method of fabricating same
US6653193B2 (en) 2000-12-08 2003-11-25 Micron Technology, Inc. Resistance variable device
US6638820B2 (en) 2001-02-08 2003-10-28 Micron Technology, Inc. Method of forming chalcogenide comprising devices, method of precluding diffusion of a metal into adjacent chalcogenide material, and chalcogenide comprising devices
US6727192B2 (en) 2001-03-01 2004-04-27 Micron Technology, Inc. Methods of metal doping a chalcogenide material
US6818481B2 (en) 2001-03-07 2004-11-16 Micron Technology, Inc. Method to manufacture a buried electrode PCRAM cell
US6734455B2 (en) 2001-03-15 2004-05-11 Micron Technology, Inc. Agglomeration elimination for metal sputter deposition of chalcogenides
US7102150B2 (en) 2001-05-11 2006-09-05 Harshfield Steven T PCRAM memory cell and method of making same
US6951805B2 (en) * 2001-08-01 2005-10-04 Micron Technology, Inc. Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry
US6737312B2 (en) 2001-08-27 2004-05-18 Micron Technology, Inc. Method of fabricating dual PCRAM cells sharing a common electrode
US6955940B2 (en) 2001-08-29 2005-10-18 Micron Technology, Inc. Method of forming chalcogenide comprising devices
US6881623B2 (en) * 2001-08-29 2005-04-19 Micron Technology, Inc. Method of forming chalcogenide comprising devices, method of forming a programmable memory cell of memory circuitry, and a chalcogenide comprising device
US6784018B2 (en) 2001-08-29 2004-08-31 Micron Technology, Inc. Method of forming chalcogenide comprising devices and method of forming a programmable memory cell of memory circuitry
US6646902B2 (en) 2001-08-30 2003-11-11 Micron Technology, Inc. Method of retaining memory state in a programmable conductor RAM
US6709958B2 (en) * 2001-08-30 2004-03-23 Micron Technology, Inc. Integrated circuit device and fabrication using metal-doped chalcogenide materials
US6815818B2 (en) 2001-11-19 2004-11-09 Micron Technology, Inc. Electrode structure for use in an integrated circuit
US6791859B2 (en) * 2001-11-20 2004-09-14 Micron Technology, Inc. Complementary bit PCRAM sense amplifier and method of operation
US6873538B2 (en) 2001-12-20 2005-03-29 Micron Technology, Inc. Programmable conductor random access memory and a method for writing thereto
US6909656B2 (en) 2002-01-04 2005-06-21 Micron Technology, Inc. PCRAM rewrite prevention
US20030143782A1 (en) 2002-01-31 2003-07-31 Gilton Terry L. Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures
KR100487519B1 (en) * 2002-02-05 2005-05-03 삼성전자주식회사 Capacitor Of Semiconductor Device And Method Of Fabricating The Same
US6867064B2 (en) 2002-02-15 2005-03-15 Micron Technology, Inc. Method to alter chalcogenide glass for improved switching characteristics
US6791885B2 (en) 2002-02-19 2004-09-14 Micron Technology, Inc. Programmable conductor random access memory and method for sensing same
US6809362B2 (en) 2002-02-20 2004-10-26 Micron Technology, Inc. Multiple data state memory cell
US6891749B2 (en) 2002-02-20 2005-05-10 Micron Technology, Inc. Resistance variable ‘on ’ memory
US7151273B2 (en) 2002-02-20 2006-12-19 Micron Technology, Inc. Silver-selenide/chalcogenide glass stack for resistance variable memory
US6847535B2 (en) 2002-02-20 2005-01-25 Micron Technology, Inc. Removable programmable conductor memory card and associated read/write device and method of operation
US7087919B2 (en) 2002-02-20 2006-08-08 Micron Technology, Inc. Layered resistance variable memory device and method of fabrication
US6937528B2 (en) 2002-03-05 2005-08-30 Micron Technology, Inc. Variable resistance memory and method for sensing same
US6849868B2 (en) 2002-03-14 2005-02-01 Micron Technology, Inc. Methods and apparatus for resistance variable material cells
US6751114B2 (en) * 2002-03-28 2004-06-15 Micron Technology, Inc. Method for programming a memory cell
US6864500B2 (en) * 2002-04-10 2005-03-08 Micron Technology, Inc. Programmable conductor memory cell structure
US6855975B2 (en) 2002-04-10 2005-02-15 Micron Technology, Inc. Thin film diode integrated with chalcogenide memory cell
US6858482B2 (en) 2002-04-10 2005-02-22 Micron Technology, Inc. Method of manufacture of programmable switching circuits and memory cells employing a glass layer
US6731528B2 (en) * 2002-05-03 2004-05-04 Micron Technology, Inc. Dual write cycle programmable conductor memory system and method of operation
US6825135B2 (en) 2002-06-06 2004-11-30 Micron Technology, Inc. Elimination of dendrite formation during metal/chalcogenide glass deposition
US6890790B2 (en) * 2002-06-06 2005-05-10 Micron Technology, Inc. Co-sputter deposition of metal-doped chalcogenides
US7015494B2 (en) 2002-07-10 2006-03-21 Micron Technology, Inc. Assemblies displaying differential negative resistance
US7209378B2 (en) 2002-08-08 2007-04-24 Micron Technology, Inc. Columnar 1T-N memory cell structure
US7018863B2 (en) 2002-08-22 2006-03-28 Micron Technology, Inc. Method of manufacture of a resistance variable memory cell
US7364644B2 (en) 2002-08-29 2008-04-29 Micron Technology, Inc. Silver selenide film stoichiometry and morphology control in sputter deposition
US7294527B2 (en) 2002-08-29 2007-11-13 Micron Technology Inc. Method of forming a memory cell
US7010644B2 (en) 2002-08-29 2006-03-07 Micron Technology, Inc. Software refreshed memory device and method
US6864521B2 (en) 2002-08-29 2005-03-08 Micron Technology, Inc. Method to control silver concentration in a resistance variable memory element
US7163837B2 (en) 2002-08-29 2007-01-16 Micron Technology, Inc. Method of forming a resistance variable memory element
US6831019B1 (en) 2002-08-29 2004-12-14 Micron Technology, Inc. Plasma etching methods and methods of forming memory devices comprising a chalcogenide comprising layer received operably proximate conductive electrodes
US6867114B2 (en) 2002-08-29 2005-03-15 Micron Technology Inc. Methods to form a memory cell with metal-rich metal chalcogenide
US6867996B2 (en) * 2002-08-29 2005-03-15 Micron Technology, Inc. Single-polarity programmable resistance-variable memory element
US6813178B2 (en) * 2003-03-12 2004-11-02 Micron Technology, Inc. Chalcogenide glass constant current device, and its method of fabrication and operation
US7022579B2 (en) * 2003-03-14 2006-04-04 Micron Technology, Inc. Method for filling via with metal
US7050327B2 (en) 2003-04-10 2006-05-23 Micron Technology, Inc. Differential negative resistance memory
US6930909B2 (en) 2003-06-25 2005-08-16 Micron Technology, Inc. Memory device and methods of controlling resistance variation and resistance profile drift
US6961277B2 (en) * 2003-07-08 2005-11-01 Micron Technology, Inc. Method of refreshing a PCRAM memory device
US7061004B2 (en) 2003-07-21 2006-06-13 Micron Technology, Inc. Resistance variable memory elements and methods of formation
US6903361B2 (en) 2003-09-17 2005-06-07 Micron Technology, Inc. Non-volatile memory structure
US7583551B2 (en) 2004-03-10 2009-09-01 Micron Technology, Inc. Power management control and controlling memory refresh operations
US7098068B2 (en) 2004-03-10 2006-08-29 Micron Technology, Inc. Method of forming a chalcogenide material containing device
US7190048B2 (en) 2004-07-19 2007-03-13 Micron Technology, Inc. Resistance variable memory device and method of fabrication
US7354793B2 (en) 2004-08-12 2008-04-08 Micron Technology, Inc. Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element
US7326950B2 (en) 2004-07-19 2008-02-05 Micron Technology, Inc. Memory device with switching glass layer
US7365411B2 (en) 2004-08-12 2008-04-29 Micron Technology, Inc. Resistance variable memory with temperature tolerant materials
US7151688B2 (en) 2004-09-01 2006-12-19 Micron Technology, Inc. Sensing of resistance variable memory devices
US7374174B2 (en) 2004-12-22 2008-05-20 Micron Technology, Inc. Small electrode for resistance variable devices
US7317200B2 (en) 2005-02-23 2008-01-08 Micron Technology, Inc. SnSe-based limited reprogrammable cell
US7427770B2 (en) 2005-04-22 2008-09-23 Micron Technology, Inc. Memory array for increased bit density
US7269044B2 (en) 2005-04-22 2007-09-11 Micron Technology, Inc. Method and apparatus for accessing a memory array
US7709289B2 (en) 2005-04-22 2010-05-04 Micron Technology, Inc. Memory elements having patterned electrodes and method of forming the same
US7269079B2 (en) 2005-05-16 2007-09-11 Micron Technology, Inc. Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory
US7233520B2 (en) 2005-07-08 2007-06-19 Micron Technology, Inc. Process for erasing chalcogenide variable resistance memory bits
US7274034B2 (en) 2005-08-01 2007-09-25 Micron Technology, Inc. Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
US7317567B2 (en) 2005-08-02 2008-01-08 Micron Technology, Inc. Method and apparatus for providing color changing thin film material
US7332735B2 (en) 2005-08-02 2008-02-19 Micron Technology, Inc. Phase change memory cell and method of formation
US7579615B2 (en) 2005-08-09 2009-08-25 Micron Technology, Inc. Access transistor for memory device
US7304368B2 (en) 2005-08-11 2007-12-04 Micron Technology, Inc. Chalcogenide-based electrokinetic memory element and method of forming the same
US7251154B2 (en) 2005-08-15 2007-07-31 Micron Technology, Inc. Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
US7277313B2 (en) 2005-08-31 2007-10-02 Micron Technology, Inc. Resistance variable memory element with threshold device and method of forming the same
US7560723B2 (en) 2006-08-29 2009-07-14 Micron Technology, Inc. Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication
US8467236B2 (en) 2008-08-01 2013-06-18 Boise State University Continuously variable resistor
JP4811520B2 (en) * 2009-02-20 2011-11-09 住友金属鉱山株式会社 Semiconductor device substrate manufacturing method, semiconductor device manufacturing method, semiconductor device substrate, and semiconductor device
US10326019B2 (en) * 2016-09-26 2019-06-18 International Business Machines Corporation Fully-depleted CMOS transistors with U-shaped channel
CN109856510B (en) * 2018-12-24 2021-02-19 内蒙古电力(集团)有限责任公司内蒙古电力科学研究院分公司 Method for searching turn-to-turn insulation defect position of dry-type air-core reactor

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02166760A (en) * 1988-12-21 1990-06-27 Matsushita Electric Ind Co Ltd Semiconductor storage device
JPH02203557A (en) * 1989-02-02 1990-08-13 Matsushita Electric Ind Co Ltd Semiconductor storage device and its manufacture
US5049517A (en) * 1990-11-07 1991-09-17 Micron Technology, Inc. Method for formation of a stacked capacitor
US5068199A (en) * 1991-05-06 1991-11-26 Micron Technology, Inc. Method for anodizing a polysilicon layer lower capacitor plate of a DRAM to increase capacitance
JPH03266460A (en) * 1990-03-15 1991-11-27 Sanyo Electric Co Ltd Manufacture of semiconductor device
US5082797A (en) * 1991-01-22 1992-01-21 Micron Technology, Inc. Method of making stacked textured container capacitor
US5110752A (en) * 1991-07-10 1992-05-05 Industrial Technology Research Institute Roughened polysilicon surface capacitor electrode plate for high denity dram
US5138411A (en) * 1991-05-06 1992-08-11 Micron Technology, Inc. Anodized polysilicon layer lower capacitor plate of a dram to increase capacitance
US5227651A (en) * 1991-03-23 1993-07-13 Samsung Electronics, Co., Ltd. Semiconductor device having a capacitor with an electrode grown through pinholes
US5519238A (en) * 1991-10-02 1996-05-21 Industrial Technology Research Institute Rippled polysilicon surface capacitor electrode plate for high density dram
US5623243A (en) * 1990-03-20 1997-04-22 Nec Corporation Semiconductor device having polycrystalline silicon layer with uneven surface defined by hemispherical or mushroom like shape silicon grain

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930009593B1 (en) * 1991-01-30 1993-10-07 삼성전자 주식회사 Lsi semiconductor memory device and manufacturing method thereof

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02166760A (en) * 1988-12-21 1990-06-27 Matsushita Electric Ind Co Ltd Semiconductor storage device
JPH02203557A (en) * 1989-02-02 1990-08-13 Matsushita Electric Ind Co Ltd Semiconductor storage device and its manufacture
JPH03266460A (en) * 1990-03-15 1991-11-27 Sanyo Electric Co Ltd Manufacture of semiconductor device
US5623243A (en) * 1990-03-20 1997-04-22 Nec Corporation Semiconductor device having polycrystalline silicon layer with uneven surface defined by hemispherical or mushroom like shape silicon grain
US5049517A (en) * 1990-11-07 1991-09-17 Micron Technology, Inc. Method for formation of a stacked capacitor
US5082797A (en) * 1991-01-22 1992-01-21 Micron Technology, Inc. Method of making stacked textured container capacitor
US5227651A (en) * 1991-03-23 1993-07-13 Samsung Electronics, Co., Ltd. Semiconductor device having a capacitor with an electrode grown through pinholes
US5068199A (en) * 1991-05-06 1991-11-26 Micron Technology, Inc. Method for anodizing a polysilicon layer lower capacitor plate of a DRAM to increase capacitance
US5138411A (en) * 1991-05-06 1992-08-11 Micron Technology, Inc. Anodized polysilicon layer lower capacitor plate of a dram to increase capacitance
US5110752A (en) * 1991-07-10 1992-05-05 Industrial Technology Research Institute Roughened polysilicon surface capacitor electrode plate for high denity dram
US5519238A (en) * 1991-10-02 1996-05-21 Industrial Technology Research Institute Rippled polysilicon surface capacitor electrode plate for high density dram

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Ema et al "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs" IEDM Tech. Digest, 1988, pp. 592-595.*
S. Inoue et al "A Spread Stacked Capacitor (SSC) Cell for 64 MBit DRAMs" IEDM Tech. Digest, 1989, pp. 31-34. *

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020060335A1 (en) * 1997-06-24 2002-05-23 Todd Edgar Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same
US20070012984A1 (en) * 1997-06-24 2007-01-18 Todd Edgar Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same
US7115932B2 (en) * 1997-06-24 2006-10-03 Micron Technology, Inc. Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same
US20060198179A1 (en) * 2001-04-19 2006-09-07 Micron Technology, Inc. Multi-resistive integrated circuit memory
US20030089940A1 (en) * 2001-04-19 2003-05-15 Micron Technology, Inc. Integrated circuit memory with offset capacitor
US8878274B2 (en) 2001-04-19 2014-11-04 Micron Technology, Inc. Multi-resistive integrated circuit memory
US6913966B2 (en) 2001-04-19 2005-07-05 Micron Technology Inc. Method for stabilizing or offsetting voltage in an integrated circuit
US20050219927A1 (en) * 2001-04-19 2005-10-06 Micron Technology, Inc. Method for stabilizing or offsetting voltage in an integrated circuit
US20030089941A1 (en) * 2001-04-19 2003-05-15 Micron Technology, Inc. Method for stabilizing or offsetting voltage in an integrated circuit
US7109545B2 (en) 2001-04-19 2006-09-19 Micron Technology, Inc. Integrated circuit memory with offset capacitor
US8093643B2 (en) 2001-04-19 2012-01-10 Micron Technology, Inc. Multi-resistive integrated circuit memory
US20100073993A1 (en) * 2001-04-19 2010-03-25 Baker R Jacob Multi-resistive integrated circuit memory
US7642591B2 (en) 2001-04-19 2010-01-05 Micron Technology, Inc. Multi-resistive integrated circuit memory
US20030045069A1 (en) * 2001-08-30 2003-03-06 Brent Gilgen Capacitor for use in an integrated circuit
US7115970B2 (en) 2001-08-30 2006-10-03 Micron Technology, Inc. Capacitor for use in an integrated circuit
US20050090070A1 (en) * 2001-08-30 2005-04-28 Micron Technology, Inc. Capacitor for use in an integrated circuit
US6888217B2 (en) 2001-08-30 2005-05-03 Micron Technology, Inc. Capacitor for use in an integrated circuit

Also Published As

Publication number Publication date
US5238862A (en) 1993-08-24
US5300801A (en) 1994-04-05

Similar Documents

Publication Publication Date Title
USRE37505E1 (en) Stacked capacitor construction
US5962885A (en) Method of forming a capacitor and a capacitor construction
US5498562A (en) Semiconductor processing methods of forming stacked capacitors
US5706164A (en) Method of fabricating high density integrated circuits, containing stacked capacitor DRAM devices, using elevated trench isolation and isolation spacers
US5170233A (en) Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor
KR0132859B1 (en) Method for manufacturing capacitor of semiconductor
JP2677490B2 (en) Method for manufacturing semiconductor memory device
KR940006682B1 (en) Method of fabricating a semiconductor memory device
US5716883A (en) Method of making increased surface area, storage node electrode, with narrow spaces between polysilicon columns
JP3501297B2 (en) Method for manufacturing semiconductor memory device
US6259127B1 (en) Integrated circuit container having partially rugged surface
US5843822A (en) Double-side corrugated cylindrical capacitor structure of high density DRAMs
US6624018B1 (en) Method of fabricating a DRAM device featuring alternate fin type capacitor structures
US6395602B2 (en) Method of forming a capacitor
GB2324408A (en) Forming DRAM cells
JPH06334144A (en) Preparation of capacitor for semiconductor memory
US5451537A (en) Method of forming a DRAM stack capacitor with ladder storage node
US5909621A (en) Single-side corrugated cylindrical capacitor structure of high density DRAMs
US6143605A (en) Method for making a DRAM capacitor using a double layer of insitu doped polysilicon and undoped amorphous polysilicon with HSG polysilicon
US20020102807A1 (en) Method for forming storage node electrode of semiconductor device
US6103571A (en) Method for forming a DRAM capacitor having improved capacitance and device formed
JP2622243B2 (en) Method of manufacturing stack capacitor for semiconductor device
US6136716A (en) Method for manufacturing a self-aligned stacked storage node DRAM cell
US6087217A (en) Method for improving capacitance in DRAM capacitors and devices formed
US5792688A (en) Method to increase the surface area of a storage node electrode, of an STC structure, for DRAM devices, via formation of polysilicon columns

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 12