JPH02203557A - Semiconductor storage device and its manufacture - Google Patents
Semiconductor storage device and its manufactureInfo
- Publication number
- JPH02203557A JPH02203557A JP1024194A JP2419489A JPH02203557A JP H02203557 A JPH02203557 A JP H02203557A JP 1024194 A JP1024194 A JP 1024194A JP 2419489 A JP2419489 A JP 2419489A JP H02203557 A JPH02203557 A JP H02203557A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- charge storage
- charge storing
- wrinkles
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 3
- 239000010703 silicon Substances 0.000 claims abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 2
- 230000037303 wrinkles Effects 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims 1
- 239000007788 liquid Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 230000001443 photoexcitation Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業−Ｊ−の利用分野
本発明は、高速で高密度な半導体記憶装置およびその製
造方法に関するものである。従来、例えばスタック型と
よばれるＤＲＡＭメモリセルにおいて電荷蓄積側電極ポ
リシリコンは、第３図にその断面を示すように特別電荷
蓄積電極４の表面に微細なしわが加工されることはなか
った。DETAILED DESCRIPTION OF THE INVENTION Field of Application of Industry-J- The present invention relates to a high-speed, high-density semiconductor memory device and a method for manufacturing the same. Conventionally, in a DRAM memory cell called a stack type, fine wrinkles have not been formed on the surface of the charge storage side electrode polysilicon of the special charge storage electrode 4, as shown in the cross section of FIG. 3.
発明が解決しようとする課題
従来の方法であれば、高密度化が進むに従１、て、容量
が減少し、高密度化あるいは高速化に限界があったＯ
課題を解決するための手段
本発明は、電荷蓄積電極の微細なしわを形成するために
、光の干渉縞を利用するか、あるいはレヂストに含まれ
た粒によるマスク端の凹凸を電荷蓄積電極に転写するこ
と特徴とするものである。Problems to be Solved by the Invention With conventional methods, as density increases, the capacity decreases and there is a limit to increasing density or speed.Means for Solving the Problems The invention is characterized in that in order to form fine wrinkles on the charge storage electrode, interference fringes of light are used or irregularities on the edge of the mask due to particles contained in the resist are transferred to the charge storage electrode. be.
作用
本発明によれば、電荷蓄積電極の表面積を、面積や体積
の増大することなく拡大することが可能となる。According to the present invention, the surface area of the charge storage electrode can be expanded without increasing the area or volume.
実施例
第１図は本発明を平面スタックとよばれるＤＲＡＭセル
に適応した実施例である。ポリシリコンの電荷蓄積電極
４形成後、上方より光照射中に、シリコンの光励起ＣＶ
Ｄを行なうと、光の干渉効果により定在波が上記電極４
表面にたち、光強度の強いところはポリシリコンがデポ
レ、弱いと２３はデポレないので、同図に示したように
、上記電極４表面上にしわが形成される。また、この光
の干渉によりしわが形成される様子を示すために、第２
図に光の干渉効果によりレヂスト上に形成されたしわを
示す。Embodiment FIG. 1 shows an embodiment in which the present invention is applied to a DRAM cell called a planar stack. After forming the charge storage electrode 4 of polysilicon, photoexcitation CV of the silicon is applied during light irradiation from above.
When step D is performed, a standing wave is generated by the above electrode 4 due to the interference effect of light.
On the surface, polysilicon is deposited where the light intensity is strong, and where it is weak, it is not deposited, so that wrinkles are formed on the surface of the electrode 4, as shown in the figure. In addition, in order to show how wrinkles are formed due to the interference of this light, the second
The figure shows wrinkles formed on the resist due to light interference effects.
また別の方法として第１図で、電荷蓄積電極４をドライ
エッチにより形成する際ドライエッチマスクを形成する
ためのレヂストに細かい粒をあえて含ませると、マスク
端に凹凸が生じ、ドライエッチによりこの凹凸が上記電
荷蓄積電極４の側面に転写され、第１図と異なり縦方向
のしわが形成される。As another method, as shown in FIG. 1, if fine grains are deliberately included in the resist for forming the dry etch mask when forming the charge storage electrode 4 by dry etching, unevenness will occur at the edge of the mask, and the dry etching will remove these irregularities. The unevenness is transferred to the side surface of the charge storage electrode 4, and unlike FIG. 1, vertical wrinkles are formed.
発明の効果
本発明によれば、電極の空間的面積、体積の増大なく、
表面積を増大でき、すなわち蓄積容量を増大でき、半導
体記憶装置及びその製造方法として実用的にきわめて有
用である。Effects of the Invention According to the present invention, there is no increase in the spatial area or volume of the electrode;
It is possible to increase the surface area, that is, increase the storage capacity, and is extremely useful in practical terms as a semiconductor memory device and its manufacturing method.
第１図は、本発明を平面型スタックとよばれるＤＲＡＭ
セルに適用した例−の断面構造図、第２図は、本発明で
用いた光の干渉効果を例示するためにレヂストにおける
光の定在波形成によるしわの形成を示す斜視図、第３図
は、従来のＤＲＡＭセルの断面構造図である。
１・・・・ビット線、４・・・・電荷蓄積電極、５・・
・・ワード線、８ａ・・・・しわのある薄い絶縁膜。
代理人の氏名 弁理士 粟野重孝 はか１名＠２図
１ 図FIG. 1 shows the present invention in a DRAM called a planar stack.
FIG. 2 is a cross-sectional structural diagram of an example applied to a cell, and FIG. 3 is a perspective view showing the formation of wrinkles due to the formation of a standing wave of light in a resist to illustrate the interference effect of light used in the present invention. 1 is a cross-sectional structural diagram of a conventional DRAM cell. 1... Bit line, 4... Charge storage electrode, 5...
...Word line, 8a...A thin insulating film with wrinkles. Name of agent: Patent attorney Shigetaka Awano 1 person @ 2 Figure 1 Figure
Claims (4)
メモリにおいて、電荷蓄積側電極シリコン表面に微細な
しわをつけた半導体記憶装置。(1) A semiconductor memory device in which fine wrinkles are formed on the silicon surface of the charge storage side electrode in a dynamic memory with one transistor and one capacitor cell.
の干渉縞を利用して形成することを特徴とする半導体記
憶装置の製造方法。(2) A method of manufacturing a semiconductor memory device, characterized in that the wrinkles of the charge storage electrode are formed using interference fringes of light by a photo-excited CVD method.
を特徴とする請求項２に記載の半導体記憶装置の製造方
法。(3) The method for manufacturing a semiconductor memory device according to claim 2, wherein a liquid source is used in the optically excited CVD method.
よるパターン端部の凹凸を電荷蓄積側電極に転写するこ
とにより形成することを特徴とする半導体記憶装置の製
造方法。(4) A method for manufacturing a semiconductor memory device, characterized in that wrinkles on the charge storage electrode are formed by transferring unevenness at the end of the pattern due to grains contained in the resist to the charge storage side electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1024194A JPH02203557A (en) | 1989-02-02 | 1989-02-02 | Semiconductor storage device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1024194A JPH02203557A (en) | 1989-02-02 | 1989-02-02 | Semiconductor storage device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02203557A true JPH02203557A (en) | 1990-08-13 |
Family
ID=12131515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1024194A Pending JPH02203557A (en) | 1989-02-02 | 1989-02-02 | Semiconductor storage device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02203557A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5300801A (en) * | 1992-03-18 | 1994-04-05 | Micron Technology, Inc. | Stacked capacitor construction |
-
1989
- 1989-02-02 JP JP1024194A patent/JPH02203557A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5300801A (en) * | 1992-03-18 | 1994-04-05 | Micron Technology, Inc. | Stacked capacitor construction |
| USRE37505E1 (en) * | 1992-03-18 | 2002-01-15 | Micron Technology, Inc. | Stacked capacitor construction |
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