US20070012984A1 - Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same - Google Patents

Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same Download PDF

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US20070012984A1
US20070012984A1 US11/510,113 US51011306A US2007012984A1 US 20070012984 A1 US20070012984 A1 US 20070012984A1 US 51011306 A US51011306 A US 51011306A US 2007012984 A1 US2007012984 A1 US 2007012984A1
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container
region
contact
substrate
portion
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US11/510,113
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Todd Edgar
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Todd Edgar
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Priority to US08/881,737 priority Critical patent/US5970340A/en
Priority to US09/317,703 priority patent/US20010022376A1/en
Priority to US9565900A priority
Priority to US09/971,242 priority patent/US6410380B2/en
Priority to US10/044,178 priority patent/US7115932B2/en
Application filed by Todd Edgar filed Critical Todd Edgar
Priority to US11/510,113 priority patent/US20070012984A1/en
Publication of US20070012984A1 publication Critical patent/US20070012984A1/en
Application status is Abandoned legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/1052Memory structures and multistep manufacturing processes therefor not provided for in groups H01L27/1055 - H01L27/112
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device and its method of fabrication are provided. The semiconductor device includes a substrate, a patterning stop region, an insulating overlayer, a container region within the insulating overlayer, a charge storage lamina or conductive layer over an interior surface of the container region; a contact region defined by the charge storage lamina or conductive layer; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the charge storage lamina or conductive layer occupy collectively substantially all of the container region. A bit line terminal is coupled to the charge storage lamina through a switching structure. According to one embodiment of the present invention, a central patterning stop region and a pair of lateral patterning stop regions are provided such that the container region defines a container cross section having an upper container portion and a lower container portion, wherein the lower container portion is positioned between the lateral stop regions, and wherein the upper container portion is wider than the lower container portion.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. patent application Ser. No. 10/044,178, filed Jan. 10, 2002 (now allowed), which is a continuation of U.S. patent application Ser. No. 09/971,242, filed Oct. 4, 2001 (now U.S. Pat. No. 6,410,380), which is a continuation of U.S. patent application Ser. No. 09/565,900 filed May 5, 2000 (now abandoned), which is a division of U.S. patent application Ser. No. 09/317,703 filed May 24, 1999 (now abandoned), which is a division of U.S. patent application Ser. No. 08/881,737 (now U.S. Pat. No. 5,970,340). U.S. patent application Ser. No. 09/317,703 is a related application.
  • BACKGROUND OF THE INVENTION
  • The present invention relates to the field of semiconductor manufacture and, more particularly, to a semiconductor device, e.g., a dynamic random access memory, incorporating an external electrical contact to a conductive layer, e.g., a cell plate of a capacitive storage cell, formed in the interior of the semiconductor device.
  • A dynamic random access memory (DRAM) chip is an example of a semiconductor device where reliable electrical contacts to an internal conductive layer must be provided. A DRAM chip is a rectangular array of individual circuits organized to store binary information through storage of different levels of voltage in a capacitive charge storage region of the DRAM chip. A transistor structure, including a plurality of transistors, is provided in the DRAM chip to provide access to the charge stored in each charge storage region. Each transistor functions as an on-off switch to open the communication lines between the charge storage region and a microprocessor in communication with the DRAM chip.
  • A network of electrically conductive cell plate contacts must be provided within the structure of the DRAM chip to enable storage of non-zero voltage levels in each charge storage region. Reliable storage is directly dependent upon the integrity of the cell plate contact. Accordingly, it is necessary to provide cell or top plate contacts characterized by low contact resistance.
  • Accordingly, there is a continuing need for semiconductor devices incorporating reliable electrical contacts to internal conductive layers.
  • SUMMARY OF THE INVENTION
  • This need is met by the present invention wherein a semiconductor device, e.g., a dynamic random access memory, is provided incorporating a reliable electrical contact to a conductive layer within the semiconductor device, e.g., a cell or top plate of a capacitive storage cell.
  • In accordance with one embodiment of the present invention, a method of fabricating a storage container structure is provided comprising the steps of: providing a substrate including a semiconductor structure; forming a patterning stop region; forming an insulating overlayer over a first surface of the substrate and over the patterning stop region; patterning a container region within the insulating overlayer such that the container region defines a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by the container side walls and the container bottom wall, and such that the container bottom wall is at least partially defined by a surface of the patterning stop region; layering a first conductive film over an interior surface of the container region; layering an intermediate insulating film over the first conductive film; layering a second conductive film over the intermediate insulating film such that the second conductive film includes a first film portion characterized by a first film thickness and a second film portion characterized by a second film thickness, such that the second film thickness is greater than the first film thickness, and such that the second film portion occupies at least a portion of the container interior; patterning a contact region in the second film portion of the second conductive film; and forming an electrical contact in the contact region such that respective portions of the electrical contact, the second conductive film, the intermediate insulating film, and the first conductive film occupy collectively at least a portion of the container region.
  • The respective portions of the electrical contact, the second conductive film, the intermediate insulating film, and the first conductive film preferably occupy collectively substantially all of the container region. The patterning stop region may be formed over the first surface of the substrate, within the substrate, or on the substrate. The container region is preferably patterned such that it further defines an upper boundary of the container cross section and the second conductive film is preferably layered such that the second film portion extends from the intermediate insulating film to at least the upper boundary of the container region. The contact region is preferably patterned, and the electrical contact is formed, such that the contact region and the electrical contact extend into the container region beyond the second film portion of the second conductive film.
  • In accordance with another embodiment of the present invention, a method of fabricating a storage container structure is provided comprising the steps of: providing a substrate including a semiconductor structure; forming a patterning stop region; forming an insulating overlayer over a first surface of the substrate and over the patterning stop region; patterning a container region within the insulating overlayer by removing a portion of an upper overlayer surface, a portion of an intermediate overlayer portion, and a portion of a lower overlayer surface such that (i) the container region defines a container cross section having container side walls, a container bottom wall, an upper container boundary, and a container interior bounded by the upper container boundary, the container side walls, and the container bottom wall, (ii) the upper container boundary is defined by the removed portion of the upper overlayer surface, (iii) the container side walls are defined by the insulating overlayer, and (iv) the container bottom wall is at least partially defined by a surface of the patterning stop region; layering a first conductive film over an interior surface of the container region; layering an intermediate insulating film over the first conductive film; layering a second conductive film over the intermediate insulating film such that the second conductive film includes a first film portion characterized by a first film thickness and a second film portion characterized by a second film thickness, such that the second film thickness is greater than the first film thickness, and such that the second film portion occupies at least a portion of the container interior; patterning a contact region in the second film portion of the second conductive film such that the contact region extends into the container region; and forming an electrical contact in the contact region such that respective portions of the electrical contact, the second conductive film, the intermediate insulating film, and the first conductive film occupy collectively at least a portion of the container region. The respective portions of the electrical contact, the second conductive film, the intermediate insulating film, and the first conductive film preferably occupy collectively substantially all of the container region.
  • In accordance with yet another embodiment of the present invention, a method of fabricating a storage container structure is provided comprising the steps of: providing a substrate including a semiconductor structure; forming a patterning stop region such that the patterning stop region includes a central stop region, a first lateral stop region, and a second lateral stop region; forming an insulating overlayer over a first surface of the substrate and over the patterning stop region; patterning a container region within the insulating overlayer such that the container region defines a container cross section having a container bottom wall, a first side wall including a first upper side wall portion and a first lower side wall portion, and a second side wall including a second upper side wall portion and a second lower side wall portion, and such that (i) the first upper side wall portion and the second upper side wall portion define an upper container portion therebetween, (ii) the first lower side wall portion and the second lower side wall portion define a lower container portion therebetween, (iii) the upper container portion is wider than the lower container portion, (iv) the container bottom wall is defined by the central stop region, (v) the first lower side wall portion is defined by a lateral surface of the first lateral stop region, and (vi) the second lower side wall portion is defined by an opposite lateral surface of the second lateral stop region; layering a first conductive film over an interior surface of the container region; layering an intermediate insulating film over the first conductive film; layering a second conductive film over the intermediate insulating film such that the second conductive film occupies at least a portion of an upper side wall region positioned between the first and second upper side wall portions; patterning a contact region in the second conductive film; and forming an electrical contact in the contact region such that respective portions of the electrical contact, the second conductive film, the intermediate insulating film, and the first conductive film occupy collectively at least a portion of the container region.
  • Respective portions of the electrical contact, the second conductive film, the intermediate insulating film, and the first conductive film preferably occupy collectively substantially all of the container region. The central stop region may be formed within the substrate and the first and second lateral stop regions may be formed over the first surface of the substrate.
  • In accordance with yet another embodiment of the present invention, a method of fabricating a storage container structure is provided comprising the steps of: providing a substrate including a semiconductor structure; forming a central patterning stop region; forming a pair of lateral patterning stop regions over a first surface of the substrate such that the lateral patterning stop regions form a substrate topography, the substrate topography including a central void positioned between the lateral patterning stop regions and over the central patterning stop region; forming an insulating overlayer over the first surface of the substrate and over the central and lateral patterning stop regions; patterning a container region within the insulating overlayer such that the container region defines a container cross section having an upper container portion and a lower container portion, such that the lower container portion is positioned within the central void, and such that the upper container portion is wider than the lower container portion; layering a first conductive film over an interior surface of the container region; layering an intermediate insulating film over an interior surface of the container region to define a back fill region such that the back fill region is bounded in part by an interior surface of the intermediate insulating film and such that the back fill region is positioned within the upper container portion; layering a second conductive film over the intermediate insulating film such that the second conductive film occupies at least a portion of the back fill region; patterning a contact region in the second conductive film such that the contact region occupies at least a portion of the upper container portion; and forming an electrical contact in the contact region such that respective portions of the electrical contact, the second conductive film, the intermediate insulating film, and the first conductive film occupy collectively at least a portion of the container region.
  • In accordance with yet another embodiment of the present invention, a method of fabricating a storage container structure is provided comprising the steps of: providing a silicon semiconductor substrate; forming a central patterning stop region within the substrate such that the central patterning stop region comprises a diffusion layer within the substrate; forming a first lateral patterning stop region over the substrate such that the first lateral patterning stop region comprises a nitride formed over a first portion of doped polysilicon; forming a second lateral patterning stop region over the substrate such that the second lateral patterning stop region comprises a nitride formed over a second portion of doped polysilicon, such that a central void is defined between the first lateral patterning stop region and the second lateral patterning stop region, and such that the central void is positioned over the central patterning stop region; forming an insulating glass overlayer over a first surface of the substrate and over the patterning stop region; selectively etching a container region within the insulating glass overlayer such that the container region defines a container cross section having a container bottom wall, a first side wall including a first upper side wall portion and a first lower side wall portion, and a second side wall including a second upper side wall portion and a second lower side wall portion, and such that (i) the first upper side wall portion and the second upper side wall portion define an upper container portion therebetween, (ii) the first lower side wall portion and the second lower side wall portion define a lower container portion therebetween, (iii) the upper container portion is wider than the lower container portion, (iv) the container bottom wall is defined by the central patterning stop region, (v) the first lower side wall portion is defined by a lateral surface of the first lateral patterning stop region, and (vi) the second lower side wall portion is defined by an opposite lateral surface of the second lateral patterning stop region; layering a first conductive polysilicon film over an interior surface of the container region; layering a dielectric hemispherical grain polysilicon film over the first conductive polysilicon film; layering a second conductive polysilicon film over the dielectric film such that the second conductive film occupies a lower side wall region positioned between the first and second lower side wall portions and at least a portion of an upper side wall region positioned between the first and second upper side wall portions; patterning a contact region in the second conductive film such that the contact region occupies at least a portion of the upper side wall region; and forming an electrical contact in the contact region such that the electrical contact extends along a substantially linear path from the lower side wall region through the upper side wall region to an exposed contact position above the container region, and such that respective portions of the electrical contact, the second conductive film, the dielectric hemispherical grain polysilicon film, and the first conductive film occupy collectively at least a portion of the container region.
  • In accordance with yet another embodiment of the present invention, a storage container structure is provided comprising: a substrate including a semiconductor structure; a patterning stop region; an insulating overlayer over a first surface of the substrate; a container region within the insulating overlayer, the container region defining a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by the container side walls and the container bottom wall, wherein the container bottom wall is at least partially defined by a surface of the patterning stop region; a charge storage lamina over an interior surface of the container region; a contact region defined by the charge storage lamina, wherein the contact region defines a contact region cross section having contact region side walls and a contact region bottom wall, and wherein the contact region side walls and the contact region bottom wall are defined by a first surface of the charge storage lamina; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the charge storage lamina occupy collectively at least a portion of the container region.
  • In accordance with yet another embodiment of the present invention, a storage container structure is provided comprising: a substrate including a semiconductor structure; a patterning stop region; an insulating overlayer over a first surface of the substrate, the insulating overlayer comprising a lower overlayer surface in contact with the substrate and the patterning stop region, an upper overlayer surface, and an intermediate overlayer portion defined between the lower overlayer surface and the upper overlayer surface; a container region within the insulating overlayer, the container region defining a container cross section having container side walls, a container bottom wall, an upper container boundary, and a container interior bounded by the container side walls, the container bottom wall, and the upper container boundary, wherein (i) the upper container boundary is continuous with the upper overlayer surface, (ii) the container side walls are defined by the insulating overlayer, and (iii) the container bottom wall is at least partially defined by a surface of the patterning stop region; a charge storage lamina over an interior surface of the container region; a contact region defined by the charge storage lamina, wherein the contact region defines a contact region cross section having contact region side walls and a contact region bottom wall, wherein the contact region side walls and the contact region bottom wall are defined by a first surface of the charge storage lamina, and wherein the contact region occupies at least a portion of the container region; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the charge storage lamina occupy collectively at least a portion of the container region.
  • In accordance with yet another embodiment of the present invention, a storage container structure is provided comprising: a substrate including a semiconductor structure; a patterning stop region, wherein the patterning stop region includes a central stop region, a first lateral stop region, and a second lateral stop region; an insulating overlayer over a first surface of the substrate; a container region within the insulating overlayer, wherein the container region defines a container cross section having a container bottom wall, a first side wall including a first upper side wall portion and a first lower side wall portion, and a second side wall including a second upper side wall portion and a second lower side wall portion, wherein (i) the first upper side wall portion and the second upper side wall portion define an upper container portion therebetween, (ii) the first lower side wall portion and the second lower side wall portion define a lower container portion therebetween, (iii) the upper container portion is wider than the lower container portion, (iv) the container bottom wall is defined by the central stop region, (v) the first lower side wall portion is defined by a lateral surface of the first lateral stop region, and (vi) the second lower side wall portion is defined by an opposite lateral surface of the second lateral stop region; a charge storage lamina over an interior surface of the container region; a contact region defined by the charge storage lamina; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the charge storage lamina occupy collectively at least a portion of the container region.
  • The respective portions of the electrical contact, the second conductive film, the intermediate insulating film, and the first conductive film preferably occupy collectively substantially all of the container region. The central stop region is preferably formed within the substrate and the first and second lateral stop regions are formed over the first surface of the substrate.
  • In accordance with yet another embodiment of the present invention, a storage container structure is provided comprising: a substrate including a semiconductor structure; a central patterning stop region; a pair of lateral patterning stop regions over a first surface of the substrate wherein a substrate topography defined by the pair of lateral patterning stop regions includes a central void positioned between the lateral patterning stop regions and over the central patterning stop region; an insulating overlayer over the first surface of the substrate; a container region within the insulating overlayer, wherein the container region defines a container cross section having an upper container portion and a lower container portion, wherein the lower container portion is positioned within the central void, and wherein the upper container portion is wider than the lower container portion; a charge storage lamina over an interior surface of the container region; a contact region defined by the charge storage lamina wherein the contact region occupies at least a portion of the upper container portion; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the charge storage lamina occupy collectively at least a portion of the container region.
  • In accordance with yet another embodiment of the present invention, a storage container structure is provided comprising: a silicon semiconductor substrate; a central patterning stop region within a first surface of the substrate, wherein the central patterning stop region comprises a diffusion layer within the substrate; a first lateral patterning stop region over the substrate, wherein the first lateral patterning stop region comprises a nitride over a first portion of doped polysilicon; a second lateral patterning stop region over the substrate, wherein the second lateral patterning stop region comprises a nitride over a second portion of doped polysilicon, wherein a central void is defined between the first lateral patterning stop region and the second lateral patterning stop region, and wherein the central void is positioned over the central patterning stop region; an insulating glass overlayer over the first surface of the substrate; a container region within the insulating glass overlayer, wherein the container region defines a container cross section having a container bottom wall, a first side wall including a first upper side wall portion and a first lower side wall portion, and a second side wall including a second upper side wall portion and a second lower side wall portion, and wherein (i) the first upper side wall portion and the second upper side wall portion define an upper container portion therebetween, (ii) the first lower side wall portion and the second lower side wall portion define a lower container portion therebetween, (iii) the upper container portion is wider than the lower container portion, (iv) the container bottom wall is defined by the central patterning stop region, (v) the first lower side wall portion is defined by a lateral surface of the first lateral patterning stop region, and (vi) the second lower side wall portion is defined by an opposite lateral surface of the second lateral patterning stop region; a first conductive polysilicon film over an interior surface of the container region; a dielectric hemispherical grain polysilicon film over the first conductive polysilicon film; a second conductive polysilicon film over the dielectric hemispherical grain polysilicon film, wherein the second conductive film occupies at least a portion of an upper side wall region positioned between the first and second upper side wall portions; a contact region in the second conductive film, wherein the contact region occupies at least a portion of the upper side wall region; and an electrical contact in the contact region, wherein the electrical contact extends along a substantially linear path from the lower side wall region through the upper side wall region to an exposed contact position above the container region, and wherein the electrical contact, the second conductive film, the dielectric hemispherical grain polysilicon film, and the first conductive film occupy collectively at least a portion of the container region.
  • In accordance with yet another embodiment of the present invention, a method of fabricating a semiconductor device is provided comprising the steps of: providing a substrate including a semiconductor structure; forming a patterning stop region; forming an insulating overlayer over a first surface of the substrate and over the patterning stop region, such that the insulating overlayer comprises a lower overlayer surface in contact with the substrate and the patterning stop region, an upper overlayer surface, and an intermediate overlayer portion defined between the lower overlayer surface and the upper overlayer surface; patterning a container region within the insulating overlayer by removing a portion of the upper overlayer surface, a portion of the intermediate overlayer portion, and a portion of the lower overlayer surface such that (i) the container region defines a container cross section having container side walls, a container bottom wall, an upper container boundary, and a container interior bounded by the upper container boundary, the container side walls, and the container bottom wall, (ii) the upper container boundary is defined by the removed portion of the upper overlayer surface, (iii) the container side walls are defined by the insulating overlayer, and (iv) the container bottom wall is at least partially defined by a surface of the patterning stop region; (v) layering a conductive film over an interior surface of the container region such that the conductive film includes a first film portion characterized by a first film thickness and a second film portion characterized by a second film thickness, such that the second film thickness is greater than the first film thickness, and such that the second film portion occupies at least a portion of the container interior; patterning a contact region in the second film portion of the conductive film such that the contact region extends into the container region; and forming an electrical contact in the contact region such that respective portions of the electrical contact and the conductive film occupy collectively at least a portion of the container region.
  • In accordance with yet another embodiment of the present invention, a method of fabricating a semiconductor device is provided comprising the steps of: providing a substrate including a semiconductor structure; forming a patterning stop region such that the patterning stop region includes a central stop region, a first lateral stop region, and a second lateral stop region; forming an insulating overlayer over a first surface of the substrate and over the patterning stop region; patterning a container region within the insulating overlayer such that the container region defines a container cross section having a container bottom wall, a first side wall including a first upper side wall portion and a first lower side wall portion, and a second side wall including a second upper side wall portion and a second lower side wall portion, and such that (i) the first upper side wall portion and the second upper side wall portion define an upper container portion therebetween, (ii) the first lower side wall portion and the second lower side wall portion define a lower container portion therebetween, (iii) the upper container portion is wider than the lower container portion, (iv) the container bottom wall is defined by the central stop region, (v) the first lower side wall portion is defined by a lateral surface of the first lateral stop region, and (vi) the second lower side wall portion is defined by an opposite lateral surface of the second lateral stop region; layering a conductive film over an interior surface of the container region such that the conductive film occupies at least a portion of an upper side wall region positioned between the first and second upper side wall portions; patterning a contact region in the conductive film; and forming an electrical contact in the contact region such that respective portions of the electrical contact and the conductive film occupy collectively at least a portion of the container region.
  • In accordance with yet another embodiment of the present invention, a semiconductor device is provided comprising: a substrate including a semiconductor structure; a patterning stop region, wherein the patterning stop region includes a central stop region, a first lateral stop region, and a second lateral stop region; an insulating overlayer over a first surface of the substrate; a container region within the insulating overlayer, wherein the container region defines a container cross section having a container bottom wall, a first side wall including a first upper side wall portion and a first lower side wall portion, and a second side wall including a second upper side wall portion and a second lower side wall portion, wherein (i) the first upper side wall portion and the second upper side wall portion define an upper container portion therebetween, (ii) the first lower side wall portion and the second lower side wall portion define a lower container portion therebetween, (iii) the upper container portion is wider than the lower container portion, (iv) the container bottom wall is defined by the central stop region, (v) the first lower side wall portion is defined by a lateral surface of the first lateral stop region, and (vi) the second lower side wall portion is defined by an opposite lateral surface of the second lateral stop region; a conductive layer over an interior surface of the container region; a contact region in the conductive film; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the conductive film occupy collectively at least a portion of the container region.
  • In accordance with yet another embodiment of the present invention, a method of fabricating a memory device is provided comprising the steps of: forming a storage container structure according to any of the embodiments of the present invention described herein; and coupling a bit line terminal to a charge storage lamina through a switching structure such that the charge storage lamina comprises the first conductive film, the intermediate insulating film, and the second conductive film, and such that a charge transfer status of the switching structure changes in response to a memory access command.
  • In accordance with yet another embodiment of the present invention, a memory device is provided comprising: a storage container structure according to any of the embodiments of the present invention described herein; and a bit line terminal coupled to the charge storage lamina through a switching structure, wherein a charge transfer status of the switching structure changes in response to a memory access command.
  • In accordance with yet another embodiment of the present invention, a method of fabricating a computer system is provided comprising the steps of: forming a storage container structure according to any of the embodiments of the present invention described herein; coupling a bit line terminal to a charge storage lamina through a switching structure such that the charge storage lamina comprises the first conductive film, the intermediate insulating film, and the second conductive film, and such that a charge transfer status of the switching structure changes in response to a memory access command; and providing a microprocessor in communication with a plurality of the storage container structures via respective ones of a plurality of the bit line terminals.
  • In accordance with yet another embodiment of the present invention, a computer system is provided comprising: a storage container structure according to any of the embodiments of the present invention described herein; a bit line terminal coupled to the charge storage lamina through a switching structure, wherein a charge transfer status of the switching structure changes in response to a memory access command; and a microprocessor in communication with a plurality of the charge storage structures via respective ones of a plurality of the bit line terminals.
  • Accordingly, it is an object of the present invention to provide semiconductor devices incorporating reliable electrical contacts to internal conductive layers of the semiconductor device.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • FIGS. 1A-1G are cross sectional views illustrating a storage container structure and its method of fabrication according to the present invention;
  • FIG. 2 is a cross sectional illustration of a storage container structure according to the present invention;
  • FIGS. 3A-3H are cross sectional views illustrating an alternative storage container structure and its method of fabrication according to the present invention;
  • FIG. 4 is a cross sectional illustration of a memory device and its method of fabrication according to the present invention;
  • FIG. 5 is a cross sectional illustration of an alternative memory device and its method of fabrication according to the present invention;
  • FIG. 6 is a cross sectional illustration of a semiconductor device and its method of fabrication; and
  • FIG. 7 is a schematic block diagram of a computer system according to the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • A method of fabricating a storage container structure 8 according to the present invention, incorporating a reliable electrical contact to an internal conductive layer of the storage container structure 8, is illustrated in FIGS. 1A-1G. Initially, a substrate 10 including a semiconductor structure 12 is provided. The semiconductor structure 12 may comprise part or all of a silicon wafer forming the substrate 10. Alternatively, the substrate 10 may be a semiconductor, an insulator, or an appropriately insulated conductor and the semiconductor structure 12 may comprise any of a variety of other materials or assemblies operative to function as a semiconductor, e.g. a semiconductor layer formed on an insulating layer, a semiconductor region formed within an insulating layer, etc.
  • Referring now to FIG. 1B, a patterning stop region 14 is formed in the substrate 10. The patterning stop region 14 comprises a material selected to prevent electrical shorting between the contact 48 and the semiconductor structure 12. Typically, the patterning stop region 14 comprises a diffusion region or an active area within the substrate 10. However, it is contemplated that the patterning stop region 14 may also comprise a material formed over the substrate 10, i.e., on or above the substrate 10. It should be noted that, for the purposes of defining the present invention, “on a substrate” refers to formation in contact with a surface of the substrate, “over a substrate” refers to formation above or in contact with a surface of the substrate, and “within a substrate” refers to formation of part or all in the interior of the substrate.
  • An insulating overlayer 16 is formed over a first surface 18 of the substrate 10 and over the patterning stop region 14 (see FIG. 1C). The insulating overlayer 16 is formed such that it comprises a lower overlayer surface 20 in contact with the substrate 10 and the patterning stop region 14, an upper overlayer surface 22, and an intermediate overlayer portion 24 defined between the lower overlayer surface 20 and the upper overlayer surface 22. The insulating overlayer 16 typically comprises a glass insulating layer, e.g., borophosphosilicate glass, but may comprise any electrically insulating layer which permits removal of portions thereof by etching, photo patterning, or another process.
  • Referring now to FIG. 1D, a container region 26 is patterned, e.g., by etching, within the insulating overlayer 16 by removing a portion of the upper overlayer surface 22, a portion of the intermediate overlayer portion 24, and a portion of the lower overlayer surface 20. The container region 26 is patterned such that it defines a container cross section having container side walls 28, a container bottom wall 30, an upper container boundary 32, and a container interior 34 bounded by the upper container boundary 32, the container side walls 28, and the container bottom wall 30. It is contemplated by the present invention that the container region 26 is likely to extend into the patterning stop region 14 as a result of the patterning process.
  • For the purpose of defining the present invention, an object or area “bounded” by a boundary or a line extends as far as but not beyond the boundary or line. An object or area is bounded in part by a boundary or line when the boundary or line limits the extent of a portion of the object or area. It is contemplated by the present invention, that structure referred to herein as a wall may include surfaces other than vertical or horizontal surfaces, e.g., inclined surfaces or surfaces having a variety of curved or linear profiles. For the purpose of defining the present invention a portion of an object includes all or part of that object.
  • The upper container boundary 32 is defined by the removed portion of the upper overlayer surface 22 such that it is continuous with the upper overlayer surface 22. The container side walls 28 are defined by portions of the insulating overlayer 16 and the container bottom wall 30 is defined by a surface of the patterning stop region 14. For the purpose of defining the present invention, a wall, boundary, surface, etc., is defined by a corresponding wall, boundary, surface, etc., when at least a portion of the corresponding wall, boundary, surface, etc., forms the defined wall, boundary, surface, etc. It is contemplated by the present invention that the dimensions of the patterning stop region 14 need not precisely correspond to the dimensions of the container bottom wall 14. The container region 26, and other areas patterned according to the present invention, are typically patterned by an etching or photo patterning process. It is contemplated by the present invention that a variety of material removal processes could be used to pattern the container region 26, e.g., wet or dry etching, ion milling, reactive ion etching, etc.
  • Referring now to FIG. 1E, a first conductive film 36 is layered over the interior surface of the container region 26 and over a portion of the upper overlayer surface 22. The interior surface is that surface of the container region 26 which is directly adjacent the container interior 34. Next, an intermediate insulating film 38 is layered over the first conductive film 36. Then, a second conductive film 40 is layered over the intermediate insulating film 38. In this manner, the components of a charge storage lamina 50 comprising the first conductive film 36, the intermediate insulating film 38, and the second conductive film 40 are provided. The first conductive film 36 and the second conductive film 40 may comprise any of a variety of conductive materials suitable for semiconductor device fabrication. For example, the conductive films 36, 40 may comprise conventional doped polysilicon films formed by sputtering, evaporation, or chemical vapor deposition. The intermediate insulating film 38 may comprise any of a variety of insulating materials operable as a dielectric material. For example, the intermediate insulating film 38 may comprise hemispherical grain polysilicon, as will be appreciated by one skilled in the art. For the purpose of defining the present invention an insulating layer or material includes layers or materials utilized in the art of semiconductor manufacture as insulating layers or dielectric layers. Similarly, a conductive layer or conductive material includes layers or materials utilized in the art of semiconductor manufacture as storage cell electrodes, connection electrodes, or other electrical connections associated with a semiconductor device.
  • The second conductive film 40 forms a back fill region 78 which is layered such that it includes a first film portion 42 characterized by a first film thickness and a second film portion 44 characterized by a second film thickness, and such that the second film thickness is greater than the first film thickness and the second film portion 44 occupies at least a portion of the container interior 34. The second conductive film 40 is layered such that the second film portion 44 extends from the intermediate insulating film 38 in the direction of the upper boundary 32 of the container region 26. The second film portion 44 occupies enough of the back fill region 78 to reduce the probability of etching into the substrate 10 during patterning of a contact region 46 in the second conductive film 40, as described below with reference to FIG. 1F. It is contemplated by the present invention that the second film thickness, which may extend up to and beyond the upper boundary 32 of the container region 26, is dependent upon the nature of the particular layering process, any subsequent patterning processes, and the particular preferences of those practicing the present invention.
  • Films are layered according to the present invention by growing or depositing material on a surface through any of a variety of layering processes, e.g., oxidation, chemical vapor deposition, evaporation, sputtering, etc. For the purpose of defining the present invention, a material which is said to occupy a space fills the space; however, a material which is said to occupy at least a portion of a space fills the space or merely fills a portion of the space. A material which is said to occupy a space may also exceed the bounds of that space.
  • Referring now to FIG. 1F, a contact region 46 is patterned in the second film portion 44 of the second conductive film 40 such that the contact region 46 extends into the container region 26. An electrical contact 48, see FIG. 1G, is then formed in the contact region 46 such that respective portions of the electrical contact 48, the second conductive film 40, the intermediate insulating film 38, and the first conductive film 36 occupy collectively a significant portion of the container region 26, and may occupy collectively substantially all of the container region 26. The electrical contact is typically a refractory metal silicide, e.g. tungsten silicide, selectively deposited into the contact region 46. It is contemplated by the present invention that a variety of material removal processes could be used to pattern the contact region 46, e.g., wet or dry etching, ion milling, reactive ion etching, etc.
  • Accordingly, a storage container structure 8 according to the present invention is illustrated in FIG. 1G, where the thicknesses and widths of the various layers and regions are not necessarily illustrated in proper scale, except where indicated herein. The storage container structure comprises the charge storage lamina 50, the electrical contact 48, the patterning stop region 14, the substrate 10, and the insulating overlayer 16. It is contemplated by the present invention that the storage container structure 8 may include further components within or adjacent any of the layers illustrated in FIG. 1G. For example, as will be appreciated by those skilled in the art, an array of metal conductive layers for making electrical contact with respective electrical contacts 48 and a passivation layer forming an uppermost surface of the storage container structure 8 are typically provided to form a complete structure.
  • The charge storage lamina 50 illustrated in FIG. 1G includes the first conductive film 36, the intermediate insulating film 38, and the second conductive film 40 structured and arranged to function as a capacitor in a manner well documented in the art. However, it is contemplated by the present invention that any of a variety of alternative charge storage laminas may be used according to the present invention. The contact region 46 occupies at least a portion of the container region 26, see FIGS. 1D, 1F, and 1G.
  • A first surface of the charge storage lamina 50 defines the contact region side walls 52 and the contact region bottom wall 54 of the contact region 46, see FIG. 1F. The electrical contact 48 formed in the contact region 46 is characterized by a low contact resistance because of the extended contact surface area defined between the electrical contact 48 and the charge storage lamina 50.
  • In the embodiment illustrated in FIG. 2, where like reference numerals refer to like elements, an alternative patterning stop region 14′ comprises an etch selective material formed over the substrate 10. For example, the alternative patterning stop region 14′ preferably comprises a silicon nitride layer 15A formed over a doped polysilicon topographic core 15B.
  • Referring now to FIGS. 3A-3H, a method of fabricating an alternative storage container structure 9 according to another embodiment of the present invention, incorporating a reliable electrical contact to an internal conductive layer of the alternative storage container structure 9, is illustrated. Initially, a substrate 10 including a semiconductor structure 12 is provided, see FIG. 3A. Subsequently, a patterning stop region including a central patterning stop region 52, a first lateral patterning stop region 54, and a second lateral patterning stop region 56, are provided, see FIGS. 3B and 3C. It is noted that for the purposes of describing the present invention, like structure is indicated with like reference numerals. A reference numeral followed by a prime indicates like structure incorporating variations in physical shape or dimension.
  • The central patterning stop region 52, see FIG. 3B, comprises an patterning stop region provided within the substrate 10. However, it is contemplated that the central patterning stop region 52 may also comprise a material formed over the substrate 10, i.e., on or above the substrate 10. Similarly, the first and second lateral patterning stop regions 54, 56, see FIG. 3C, are provided over the substrate 10 and typically comprise an etch selective material in the form of a silicon nitride layer 15A formed over a doped polysilicon topographic core 15B. However, the etch selective material may comprise any of a variety of materials which create a surface topography and which etch selectively with respect to surrounding structural materials.
  • The pair of lateral patterning stop regions 54, 56 form a substrate topography including a central void 62 positioned between the lateral patterning stop regions 54, 56 and over the central patterning stop region 52. An insulating overlayer 16 is formed over a first surface 18 of the substrate 10 and over the central and lateral patterning stop regions 52, 54, 56 (see FIG. 3D). The insulating overlayer 16 typically comprises a glass insulating layer, e.g., borophosphosilicate glass, but may comprise any electrically insulating layer which permits removal, by etching or otherwise, of portions thereof.
  • A container region 26′ is patterned within the insulating overlayer 16 such that the container region 26′ defines a container cross section having an upper container portion 64 and a lower container portion 66, see FIG. 3E. The lower container portion 66 is positioned within the central void 62 and the upper container portion 64 is wider than the lower container portion 66. A first upper side wall portion 68 and a second upper side wall portion 70 of the cross section define the upper container portion 64 therebetween. A first lower side wall portion 72 and a second lower side wall portion 74 of the cross section define the lower container portion 66 therebetween. The first lower side wall portion 72 is defined by a lateral surface 58 of the first lateral patterning stop region 54 and the second lower side wall portion 74 is defined by an opposite lateral surface 60 of the second lateral patterning stop region 56. The container bottom wall is defined by an upper surface 76 of the central patterning stop region 52. For the purpose of defining the present invention where the walls of the upper container portion 64 or the walls of the lower container portion 66 are inclined or otherwise non-vertical, the upper container portion 64 is said to be wider than the lower container portion 66 if its average width is larger than that of the lower container portion 66. It is contemplated by the present invention that the container region 26′ may extend partially into an area formerly occupied by the central patterning stop region 52 as a result of the particular patterning process utilized to create the container region 26′. It is contemplated by the present invention that the first and second lateral patterning stop regions 54, 56 and the central patterning stop region 52 may include an additional layer of material positioned thereon such that the additional layer defines the container region 26′. For example, a relatively thin layer of unremoved insulating overlayer 16 may be positioned between any one or all of the patterning stop regions 52, 54, 56 and the container region 26′.
  • Referring now to FIGS. 3E and 3F, a first conductive film 36′ is layered over an interior surface of the container region 26′. Next, an intermediate insulating film 38′ is layered over the first conductive film 36′ to define a back fill region 78′. The back fill region 78′ is bounded by an interior surface of the intermediate insulating film 38′ and is positioned within the upper container portion 64 and the lower container portion 66. A second conductive film 40′ is layered over the intermediate insulating film 38′ such that the second conductive film 40′ occupies a lower side wall region 80 and at least a portion of an upper side wall region 82 of the back fill region 78′. The lower side wall region 80 is narrower than the upper side wall region 82. In this manner, the components of a charge storage lamina 50′ comprising the first conductive film 36′, the intermediate insulating film 38′, and the second conductive film 40′ are provided.
  • The extent to which the second conductive film 40′ occupies the upper side wall region 82 may be controlled by controlling the spacing of the first and second lateral patterning stop regions 54, 56. The extent to which the second conductive film 40′ occupies the upper side wall region 82 is also dependent upon the nature of the particular layering process, any subsequent patterning processes, and the particular preferences of those practicing the present invention. The second conductive film 40′ occupies enough of the back fill region 78′ to reduce the probability of etching into the substrate 10 during patterning of a contact region 46′ in the second conductive film 40, as described below with reference to FIG. 3G.
  • As shown in FIG. 3G, a contact region 46′ is patterned in the second conductive film 40′ such that the contact region 46′ occupies at least a portion of the upper side wall region 82 and the upper container portion 64 and may extend into the lower side wall region 80 and the lower container portion 66.
  • An electrical contact 48′ is formed in the contact region 46′ to extend, preferably along a substantially linear path, from the lower side wall region 80 through the upper side wall region 82 to an exposed contact position 88 above the container region 26′, see FIG. 3H. Respective portions of the electrical contact 48′, the second conductive film 40′, the intermediate insulating film 38′, and the first conductive film 36′ occupy a significant portion of the container region 26′, see FIGS. 3E and 3H, and may occupy collectively substantially all of the container region 26′. For the purpose of defining the present invention, a surface or region is said to be exposed when the surface or region is not covered by another solid material.
  • Accordingly, an alternative storage container structure 9 according to the present invention is illustrated in FIG. 3H. The alternative storage container structure 9 comprises a charge storage lamina 50′, the electrical contact 48′, the pair of lateral patterning stop regions 54, 56, the central patterning stop region 52, the substrate 10, and the insulating overlayer 16. The contact region 46′ is defined by the charge storage lamina 50′. It is contemplated by the present invention that the storage container structure 9 may include further components within or adjacent any of the layers illustrated in FIG. 3H.
  • The electrical contact 48′ formed in the contact region 46′ is characterized by a low contact resistance because of the extended contact surface area defined between the electrical contact 48′ and the charge storage lamina 50′. The reduced width of the lower side wall region 80 ensures that, during production of a plurality of storage container structures 9 according to the method of the present invention, the second conductive film 40′ will reliably and consistently occupy respective lower side wall regions 80 and upper side wall regions 82 of each storage container structure 9 so produced. It is contemplated by the present invention that the spacing of the lateral patterning stop regions 54, 56, which, for example, is controlled by the respective widths of the regions 54, 56, is selected such that reliable filling of the back fill region 78′ is achieved, see FIG. 3F. As will be appreciated by those skilled in the art, the spacing may be varied according to the specific mode of manufacture utilized to practice the present invention and according to the specific device tolerances required for a particular application.
  • Referring now to FIG. 4, a memory device 6 and its method of fabrication according to the present invention are illustrated. The memory device 6 incorporates the storage container structure 8 described herein with reference to FIGS. 1A-1G. Accordingly, the storage container structure 8 portion of the memory device 6 is fabricated substantially as described herein with reference to FIGS. 1A-1G. The remainder of the memory device 6 is assembled by providing a conventional switching structure 100, in any of a number of well known manners, and by coupling a bit line terminal 102 to the charge storage lamina 50 through the switching structure 100. The charge storage lamina 50 comprises the first conductive film 36, the intermediate insulating film 38, and the second conductive film 40. The charge transfer status of the switching structure 100 changes in response to a memory access command to enable transfer of charge stored in the charge storage lamina 50 to the bit line terminal 102. As will be appreciated by those skilled in the art, the switching structure 100 preferably comprises a field effect transistor including a gate 104 and a pair of doped source/drain regions 106.
  • Referring now to FIG. 5, an alternative memory device 7 and its method of fabrication according to the present invention are illustrated. The memory device 7 incorporates the alternative storage container structure 9 described herein with reference to FIGS. 3A-3H. Accordingly, the alternative storage container structure 9 portion of the memory device 6 is fabricated substantially as described herein with reference to FIGS. 1A-1G, with the exception that the first lateral patterning stop region 54 embodies the switching structure 100 described above with reference to FIG. 4. The remainder of the memory device 7 is assembled by providing the bit line terminal 102, as described above with respect to FIG. 4. As noted above, the bit line terminal 102 is coupled to the charge storage lamina 50′ through the switching structure 100. The charge transfer status of the switching structure 100 changes in response to a memory access command to enable transfer of charge stored in the charge storage lamina 50′ to the bit line terminal 102.
  • Referring now to FIG. 6, a semiconductor device 5 and its method of fabrication are illustrated. The semiconductor device 5 and its method of manufacture are substantially the same as the alternative storage container structure 9 and the corresponding method of manufacture described herein with reference to FIGS. 3A-3H; however, the semiconductor device 5 and the corresponding method of fabrication differ in that a charge storage lamina 50′ is not provided in the semiconductor device. Rather, a conductive film 108, e.g. a conductive polysilicon film, replaces the charge storage lamina 50′. In this manner, the electrical contact 48′ formed in the contact region 46′ is characterized by a low contact resistance because of the extended contact surface area defined between the electrical contact 48′ and the conductive film 108. The reduced width of the lower side wall region 80 ensures that, during production of a plurality of semiconductor devices 5 according to the method of the present invention, the conductive film 108 will reliably and consistently occupy respective lower side wall regions 80 and upper side wall regions 82 of each semiconductor device 5 so produced.
  • Referring now to FIG. 7, it is contemplated by the present invention that the memory device 6, described in detail above with respect to FIG. 4, and the alternative memory device 7 described in detail above with respect to FIG. 5, and their respective methods of fabrication, may be utilized to provide a DRAM chip 110 within a computer system 112. As will be appreciated by those skilled in the art, the computer system 112 would include ROM 114, mass memory 116, peripheral devices 118, and I/O devices 120 in communication with a microprocessor 122 via a data bus 124 or another suitable data communication path. Specifically, referring to the memory device 6, described in detail herein with respect to FIG. 4, the memory device 6 is fabricated substantially as described, and the remainder of the computer system 112 is assembled by providing the components illustrated in FIG. 7 and by providing the microprocessor 122 in communication with a plurality of the storage container structures 8 via respective ones of a plurality of the bit line terminals 102. Similarly, referring to the alternative memory device 7, described in detail herein with respect to FIG. 5, the memory device 7 is fabricated substantially as described, and the remainder of the computer system 112 is assembled by providing the components illustrated in FIG. 7 and by providing the microprocessor 122 in communication with a plurality of the alternative storage container structures 9 via respective ones of a plurality of the bit line terminals 102.
  • Having described the invention in detail and by reference to preferred embodiments thereof, it will be apparent that modifications and variations are possible without departing from the scope of the invention defined in the appended claims.

Claims (16)

1. A memory device comprising:
a storage container structure comprising:
a substrate including a semiconductor structure;
a single layer of insulating material disposed over and in contact with said substrate, said insulating material of sufficient depth to include a container region disposed therein, said container region defining a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by said container side walls and said container bottom wall;
a patterning stop region disposed over said substrate such that all of said container bottom wall is defined by an upper surface of said patterning stop region;
a charge storage lamina formed over an interior surface of said container region, said charge storage lamina comprising a first conductive film with at least a portion thereof in contact with said patterning stop region, a second conductive film defining a first surface thereon, and an insulating film disposed intermediate said first and second conductive films;
a contact region defined by said charge storage lamina, wherein said contact region defines a contact region cross section having contact region side walls and a contact region bottom wall, and wherein said contact region side walls and said contact region bottom wall are defined by said first surface of said second conductive film; and
an electrical contact in contact with said first surface of said second conductive film such that said electrical contact and said second conductive film occupy collectively at least a portion of said container region; and
a bit line terminal coupled to said charge storage lamina through a switching structure, wherein a charge transfer status of said switching structure changes in response to a memory access command.
2. A device comprising:
a storage container structure including:
a substrate including a semiconductor structure;
a single layer of insulating material disposed over and in contact with said substrate, said insulating overlayer including a container region disposed therein, said container region defining a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by said container side walls and said container bottom wall;
a patterning stop region disposed over said substrate such that all of said container bottom wall is defined by an upper surface of said patterning stop region;
a charge storage lamina formed over an interior surface of said container region, said charge storage lamina comprising a first conductive film with at least a portion thereof in contact with said patterning stop region, a second conductive film defining a first surface thereon, and an insulating film disposed intermediate said first and second conductive films such that a shape defined by said insulating and first and second conductive films define a contact region with a cross section having side walls and a bottom wall that are formed by said first surface of said second conductive film; and
an electrical contact disposed in said contact region, wherein respective portions of said electrical contact and said second conductive film occupy collectively at least a portion of said container region; and
a bit line terminal coupled to said charge storage lamina through a switching structure, wherein a charge transfer status of said switching structure changes in response to a memory access command.
3. A memory device comprising:
a storage container structure including:
a substrate including a semiconductor structure;
a single layer of insulating material disposed over and in contact with said substrate, said insulating material of sufficient depth to include a container region disposed therein, said container region defining a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by said container side walls and said container bottom wall;
a transistor switching structure comprising a gate, a source and a drain, wherein at least one of said source and drain comprises a patterning stop region disposed over said substrate such that all of said container bottom wall is defined by an upper surface of said patterning stop region;
a capacitor formed over an interior surface of said container region, said capacitor comprising a first electrode in contact with said patterning stop region, an insulating layer disposed on top of said first electrode, and a second electrode disposed on top of said insulating layer, said capacitor configured such that a surface of said second electrode defines a contact region therein; and
an electrical contact disposed in said contact region, wherein respective portions of said electrical contact and said second electrode occupy collectively at least a portion of said container region; and
a bit line terminal coupled to said capacitor through said transistor switching structure.
4. The memory device of claim 1, wherein said substrate comprises a single layer doped substrate.
5. The memory device of claim 4, wherein said patterning stop region is in contact with said substrate.
6. The memory device of claim 5, wherein said insulating film disposed intermediate said first and second conductive films comprises a dielectric layer.
7. The device of claim 2, wherein said substrate comprises a single layer doped substrate.
8. The device of claim 7, wherein said patterning stop region is in contact with said substrate.
9. The device of claim 8, wherein said insulating film disposed intermediate said first and second conductive films comprises a dielectric layer.
10. The device of claim 9, further comprising a microprocessor in communication with a plurality of said charge storage structures via respective ones of a plurality of said bit line terminals.
11. The device of claim 10, further comprising a read-only-memory device, a mass memory device and at least one input/output device, all in signal communication with said microprocessor.
12. The device of claim 11, wherein said at least one input/output device comprises a data input device and an output viewing device.
13. (canceled)
14. (canceled)
15. The memory device of claim 16, wherein said insulating layer comprises a dielectric layer.
16. A memory device comprising:
a storage container structure including:
a single layer doped substrate including a semiconductor structure;
a single layer of insulating material disposed over and in contact with said substrate, said insulating material of sufficient depth to include a container region disposed therein, said container region defining a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by said container side walls and said container bottom wall;
a transistor switching structure comprising a gate, a source and a drain, wherein at least one of said source and drain comprises a patterning stop region disposed over said substrate such that all of said container bottom wall is defined by an upper surface of said patterning stop region, wherein a lower surface of said patterning stop region is in contact with said substrate, and lateral side surfaces of said patterning stop region are substantially surrounded by said single layer of insulating material disposed over and in contact with said substrate;
a capacitor formed over an interior surface of said container region, said capacitor comprising a first electrode in contact with said patterning stop region, an insulating layer disposed on top of said first electrode, and a second electrode disposed on top of said insulating layer, said capacitor configured such that a surface of said second electrode defines a contact region therein; and
an electrical contact disposed in said contact region, wherein respective portions of said electrical contact and said second electrode occupy collectively at least a portion of said container region; and
a bit line terminal coupled to said capacitor through said transistor switching structure.
US11/510,113 1997-06-24 2006-08-25 Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same Abandoned US20070012984A1 (en)

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US9565900A true 2000-05-05 2000-05-05
US09/971,242 US6410380B2 (en) 1997-06-24 2001-10-04 Method for making semiconductor device incorporating and electrical contact to an internal conductive layer
US10/044,178 US7115932B2 (en) 1997-06-24 2002-01-10 Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same
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US20010022376A1 (en) 2001-09-20
US20020060335A1 (en) 2002-05-23
US20050023566A1 (en) 2005-02-03
US5970340A (en) 1999-10-19
US6410380B2 (en) 2002-06-25
US20020019095A1 (en) 2002-02-14
US7115932B2 (en) 2006-10-03

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