KR880011908A - 반도체 소자 제조방법 - Google Patents
반도체 소자 제조방법 Download PDFInfo
- Publication number
- KR880011908A KR880011908A KR1019880002276A KR880002276A KR880011908A KR 880011908 A KR880011908 A KR 880011908A KR 1019880002276 A KR1019880002276 A KR 1019880002276A KR 880002276 A KR880002276 A KR 880002276A KR 880011908 A KR880011908 A KR 880011908A
- Authority
- KR
- South Korea
- Prior art keywords
- thickness
- wafer
- plasma
- initial thickness
- oxide layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims 3
- 239000004065 semiconductor Substances 0.000 title claims 3
- 238000000034 method Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 150000002500 ions Chemical class 0.000 claims 2
- 230000003647 oxidation Effects 0.000 claims 2
- 238000007254 oxidation reaction Methods 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 1
- 229910052786 argon Inorganic materials 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
- H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명에 의한 방법에 의하여 반도체 소자 제조의 몇개의 연속적인 단계를 도시한 횡단면도.
Claims (6)
- 산화 마스크가 실리콘 웨이퍼의 표면에 국부적으로 제공되고 그 후에 웨이퍼는 산화 처리가 되며 산화 마스크에 의하여 덮혀지지 않은 웨이퍼의 부분 산화에 의하여 필드 산화물층이 필요한 절연 두께와 또 다른 처리 단계 동안에 두께 손실을 보상하기 위하여 필요한 부가 두께의 합과 동일한 초기 두께로 형성되는 반도체 소자 제조방법에 있어서, 상기초기 두께를 가지는 필드 산화물층이 초기 두께에 도달할 때까지 웨이퍼가 반응 이온을 가진 플라스마에서 에치된 후에 초기 두께보다 큰 두께를 가지는 것을 특징으로 하는 반도체 소자 제조방법.
- 제1항에 있어서, 필드 산화물층이 초기두께보다 최소한 100mm 큰 두께를 가진 것을 특징으로 하는 반도체 소자 제조방법.
- 제1항 또는 제2항에 있어서, 필드 산화물층이 초기 두께보다 많아야 250mm 큰 두께를 가진 것을 특징으로 하는 반도체 소자 제조방법.
- 전항중 어는 한 항에 있어서, 실리콘 웨이퍼는 산화처리 후에 그러나 플라스마에서 에칭 처리전에 플라즈마에서 에칭 동안에 제거된 평면의 보조층으로 덮여진 것을 특징으로 하는 반도체 소자 제조방법.
- 제4항중에 있어서, 평면의 보조층과 같은 실리콘 산화물층은 테트라에톡시 시래인(tetraethoxy silane)을 포함하는 대기에서 웨이퍼를 가열에 의하여 제공되는 것을 특징으로 하는 반도체 소자 제조방법.
- 전항 중 어느 한 항에 있어서, 반응 이온을 가진 에칭 처리는 하나는 접지되고 다른 하나는 공급 소스에 접속된 평행판을 구비하는 반응기에서 수행되며 플라스마는 판 사이에서 발생되고 웨이퍼는 접지된 판상에 제공되며, 그리고 플라스마는 테트라플루오메탄(CF4) 및 판 사이를 지나는 아르곤의 혼합기체에서 발생되는 것을 특징으로 하는 반도체 소자 제조방법.※ 참고사항 : 최초출원 내용에 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL8700541 | 1987-03-06 | ||
NL8700541A NL8700541A (nl) | 1987-03-06 | 1987-03-06 | Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een plak silicium plaatselijk wordt voorzien van veldoxidegebieden. |
Publications (1)
Publication Number | Publication Date |
---|---|
KR880011908A true KR880011908A (ko) | 1988-10-31 |
Family
ID=19849667
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880002276A KR880011908A (ko) | 1987-03-06 | 1988-03-05 | 반도체 소자 제조방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4952525A (ko) |
EP (1) | EP0284124A1 (ko) |
JP (1) | JPS63228739A (ko) |
KR (1) | KR880011908A (ko) |
NL (1) | NL8700541A (ko) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3092185B2 (ja) * | 1990-07-30 | 2000-09-25 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US5290396A (en) * | 1991-06-06 | 1994-03-01 | Lsi Logic Corporation | Trench planarization techniques |
US5413966A (en) * | 1990-12-20 | 1995-05-09 | Lsi Logic Corporation | Shallow trench etch |
US5225358A (en) * | 1991-06-06 | 1993-07-06 | Lsi Logic Corporation | Method of forming late isolation with polishing |
US5248625A (en) * | 1991-06-06 | 1993-09-28 | Lsi Logic Corporation | Techniques for forming isolation structures |
US5252503A (en) * | 1991-06-06 | 1993-10-12 | Lsi Logic Corporation | Techniques for forming isolation structures |
US6432759B1 (en) * | 1992-11-24 | 2002-08-13 | Lsi Logic Corporation | Method of forming source and drain regions for CMOS devices |
JPH08316223A (ja) * | 1995-05-16 | 1996-11-29 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6008526A (en) * | 1995-05-30 | 1999-12-28 | Samsung Electronics Co., Ltd. | Device isolation layer for a semiconductor device |
US5861339A (en) * | 1995-10-27 | 1999-01-19 | Integrated Device Technology, Inc. | Recessed isolation with double oxidation |
US5672538A (en) * | 1995-12-04 | 1997-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd | Modified locus isolation process in which surface topology of the locos oxide is smoothed |
US5686346A (en) * | 1996-03-26 | 1997-11-11 | Advanced Micro Devices, Inc. | Method for enhancing field oxide thickness at field oxide perimeters |
US5652177A (en) * | 1996-08-22 | 1997-07-29 | Chartered Semiconductor Manufacturing Pte Ltd | Method for fabricating a planar field oxide region |
US5930647A (en) | 1997-02-27 | 1999-07-27 | Micron Technology, Inc. | Methods of forming field oxide and active area regions on a semiconductive substrate |
US6268266B1 (en) * | 1999-10-22 | 2001-07-31 | United Microelectronics Corp. | Method for forming enhanced FOX region of low voltage device in high voltage process |
US6268267B1 (en) * | 2000-01-24 | 2001-07-31 | Taiwan Semiconductor Manufacturing Company | Silicon-oxynitride-oxide (SXO) continuity film pad to recessed bird's beak of LOCOS |
WO2003032378A1 (de) * | 2001-10-08 | 2003-04-17 | Infineon Technologies Ag | Verfahren zum herstellen einer gate-struktur fuer einen mos-transistor |
US20040007755A1 (en) * | 2002-07-12 | 2004-01-15 | Texas Instruments Incorporated | Field oxide profile of an isolation region associated with a contact structure of a semiconductor device |
US6949448B2 (en) * | 2003-04-01 | 2005-09-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Local oxidation of silicon (LOCOS) method employing graded oxidation mask |
US20060057765A1 (en) | 2004-09-13 | 2006-03-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Image sensor including multiple lenses and method of manufacture thereof |
US20080299780A1 (en) * | 2007-06-01 | 2008-12-04 | Uv Tech Systems, Inc. | Method and apparatus for laser oxidation and reduction |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US204A (en) * | 1837-05-22 | Construction of and mode of | ||
NL173110C (nl) * | 1971-03-17 | 1983-12-01 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht. |
US4378565A (en) * | 1980-10-01 | 1983-03-29 | General Electric Company | Integrated circuit and method of making same |
US4385975A (en) * | 1981-12-30 | 1983-05-31 | International Business Machines Corp. | Method of forming wide, deep dielectric filled isolation trenches in the surface of a silicon semiconductor substrate |
JPS58147041A (ja) * | 1982-02-24 | 1983-09-01 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS58168264A (ja) * | 1982-03-30 | 1983-10-04 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS58169929A (ja) * | 1982-03-31 | 1983-10-06 | Fujitsu Ltd | 半導体装置の製造方法 |
FR2529714A1 (fr) * | 1982-07-01 | 1984-01-06 | Commissariat Energie Atomique | Procede de realisation de l'oxyde de champ d'un circuit integre |
US4539744A (en) * | 1984-02-03 | 1985-09-10 | Fairchild Camera & Instrument Corporation | Semiconductor planarization process and structures made thereby |
US4612701A (en) * | 1984-03-12 | 1986-09-23 | Harris Corporation | Method to reduce the height of the bird's head in oxide isolated processes |
ATE45248T1 (de) * | 1984-12-13 | 1989-08-15 | Siemens Ag | Verfahren zum herstellen einer die aktiven bereiche einer hochintegrierten cmos-schaltung trennenden isolation. |
NL8501720A (nl) * | 1985-06-14 | 1987-01-02 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een siliciumplak plaatselijk wordt voorzien van veldoxide met kanaalonderbreker. |
-
1987
- 1987-03-06 NL NL8700541A patent/NL8700541A/nl not_active Application Discontinuation
-
1988
- 1988-02-26 EP EP88200357A patent/EP0284124A1/en not_active Withdrawn
- 1988-02-29 JP JP63047344A patent/JPS63228739A/ja active Pending
- 1988-03-05 KR KR1019880002276A patent/KR880011908A/ko not_active Application Discontinuation
-
1989
- 1989-12-11 US US07/453,092 patent/US4952525A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US4952525A (en) | 1990-08-28 |
JPS63228739A (ja) | 1988-09-22 |
NL8700541A (nl) | 1988-10-03 |
EP0284124A1 (en) | 1988-09-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |