KR940004751A - 트렌치 측벽의 선택적 산화방법 - Google Patents

트렌치 측벽의 선택적 산화방법 Download PDF

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Publication number
KR940004751A
KR940004751A KR1019930015416A KR930015416A KR940004751A KR 940004751 A KR940004751 A KR 940004751A KR 1019930015416 A KR1019930015416 A KR 1019930015416A KR 930015416 A KR930015416 A KR 930015416A KR 940004751 A KR940004751 A KR 940004751A
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KR
South Korea
Prior art keywords
trench
etching
oxide layer
primary oxide
kev
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KR1019930015416A
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English (en)
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KR100273902B1 (ko
Inventor
레-얀
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프레데릭 얀 스미트
필립스 일렉트로닉스 엔. 브이.
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Publication of KR940004751A publication Critical patent/KR940004751A/ko
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Publication of KR100273902B1 publication Critical patent/KR100273902B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/163—Thick-thin oxides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 실리콘 기판내의 트렌치 측벽들을 선택적으로 산화시키는 기술에 관한 것이다. 이들 측벽은 트랜치 IC의 요건에 맞도록 제각기 상이한 두께로 산화될 수 있다.

Description

트렌치 측벽의 선택적 산화방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도면은 본 발명의 수행시에 얻어지는 구조의 예를 도시한 도면.

Claims (8)

  1. (a)트렌치의 전표면 영역위에 1차 산화물층을 제1두께까지 성장시키는 단계와; (b)상기 1차 산화물층위에 질화실리콘을 침적시키는 단계와; (c)상기 트렌치의 선택적 측벽상의 상기 질화실리콘 부분을 제거하여 상기1차 산화물층을 노출시키는 단계와; (d)상기 1차 산화물층의 노출부분을 에칭하는 단계와; (e)상기 에칭된 노츨부분을 상기 제1두께와는 다른 제2 두께까지 선택적으로 산화시키는 단계를; 포함하는 트렌치 측벽의 선택적 산화방법.
  2. 제1항에 있어서, 상기 (c) 내지 (e)단계를 반복하여 상기 트렌치의 여러 다른 측벽들을 여러 다른 두께로 선택적으로 산화시키는 방법.
  3. 제1항에 있어서, 상기 단계(c)를 이온 밀링이나 반응성 이온 빔 에칭(RIBE)으로 수행하는 방법.
  4. 제1항에 있어서, 상기 단계(c)는 먼저 상기 트렌치의 상기 선택된 측벽상의 상기 질화실리콘부분을 이온에 의해 손상시키는 손상단계와 그 손상부분을 에칭하는 에칭단계로 이루어진 방법.
  5. 제4항에 있어서, 상기 손상 단계를 붕소 이온을 사용하는 이온 충격법에 의해 수행하는 방법.
  6. 제5항에 있어서, 상기 이온 충격법을 40keV, 80keV 또는 120keV에서 수행하는 방법.
  7. 제4항에 있어서, 상기 손상부분의 에칭을 고온 H3PO4에서 수행하는 방법.
  8. 제1항에 있어서. 상기 단계(c)를 사전설정된 각도에서 이온 충격법에 의해 수행하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930015416A 1992-08-12 1993-08-09 트렌치 측벽의 선택적 산화방법 KR100273902B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US929,086 1992-08-12
US07/929,086 US5240875A (en) 1992-08-12 1992-08-12 Selective oxidation of silicon trench sidewall

Publications (2)

Publication Number Publication Date
KR940004751A true KR940004751A (ko) 1994-03-15
KR100273902B1 KR100273902B1 (ko) 2000-12-15

Family

ID=25457299

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930015416A KR100273902B1 (ko) 1992-08-12 1993-08-09 트렌치 측벽의 선택적 산화방법

Country Status (5)

Country Link
US (1) US5240875A (ko)
EP (1) EP0592024B1 (ko)
JP (1) JPH06177238A (ko)
KR (1) KR100273902B1 (ko)
DE (1) DE69322053T2 (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5824580A (en) * 1996-07-30 1998-10-20 International Business Machines Corporation Method of manufacturing an insulated gate field effect transistor
US5757059A (en) * 1996-07-30 1998-05-26 International Business Machines Corporation Insulated gate field effect transistor
US5721448A (en) * 1996-07-30 1998-02-24 International Business Machines Corporation Integrated circuit chip having isolation trenches composed of a dielectric layer with oxidation catalyst material
US6348394B1 (en) 2000-05-18 2002-02-19 International Business Machines Corporation Method and device for array threshold voltage control by trapped charge in trench isolation
DE10115912A1 (de) * 2001-03-30 2002-10-17 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiteranordnung und Verwendung einer Ionenstrahlanlage zur Durchführung des Verfahrens
DE10143997B4 (de) * 2001-09-07 2006-12-14 Infineon Technologies Ag Verfahren zur Herstellung einer integrierten Halbleiterschaltung mit einem Isolationsgraben
US6661068B2 (en) * 2002-03-20 2003-12-09 Semiconductor Components Industries Llc Semiconductor device and method of providing regions of low substrate capacitance
TW200416772A (en) * 2002-06-06 2004-09-01 Asml Us Inc System and method for hydrogen-rich selective oxidation
US6750116B1 (en) * 2003-07-14 2004-06-15 Nanya Technology Corp. Method for fabricating asymmetric inner structure in contacts or trenches
KR102422284B1 (ko) * 2014-07-03 2022-07-15 어플라이드 머티어리얼스, 인코포레이티드 선택적인 증착을 위한 방법 및 장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4437226A (en) * 1981-03-02 1984-03-20 Rockwell International Corporation Process for producing NPN type lateral transistor with minimal substrate operation interference
NL8301262A (nl) * 1983-04-11 1984-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij met behulp van ionenimplantatie patronen worden aangebracht in een laag siliciumnitride.
EP0218039B1 (de) * 1985-09-30 1990-11-07 Siemens Aktiengesellschaft Verfahren zur Übertragung feinster Fotolackstrukturen
NL8502765A (nl) * 1985-10-10 1987-05-04 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
US5182227A (en) * 1986-04-25 1993-01-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
DE3736531A1 (de) * 1986-10-30 1988-05-11 Mitsubishi Electric Corp Verfahren zur herstellung einer halbleitereinrichtung
JPS6464336A (en) * 1987-09-04 1989-03-10 Toshiba Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
KR100273902B1 (ko) 2000-12-15
US5240875A (en) 1993-08-31
EP0592024B1 (en) 1998-11-11
DE69322053T2 (de) 1999-05-27
EP0592024A1 (en) 1994-04-13
DE69322053D1 (de) 1998-12-17
JPH06177238A (ja) 1994-06-24

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