KR880010362A - 어드레스 라인 오류 테스트 방법 - Google Patents

어드레스 라인 오류 테스트 방법 Download PDF

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Publication number
KR880010362A
KR880010362A KR1019880001348A KR880001348A KR880010362A KR 880010362 A KR880010362 A KR 880010362A KR 1019880001348 A KR1019880001348 A KR 1019880001348A KR 880001348 A KR880001348 A KR 880001348A KR 880010362 A KR880010362 A KR 880010362A
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address
bit
bits
card
test
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KR1019880001348A
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KR920001104B1 (ko
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죤 애쉬 케빈
하베이 더렌버거 잭
로니 파슨즈 레이몬드
Original Assignee
하워드 지.피거로아
인터내셔널 비지네스 머신즈 코포레이션
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Publication of KR880010362A publication Critical patent/KR880010362A/ko
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/1052—Bypassing or disabling error detection or correction

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Slot Machines And Peripheral Devices (AREA)
  • Credit Cards Or The Like (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)

Abstract

내용 없음

Description

어드레스 라인 오류 테스트 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 테스트 방법을 지원하게 될 메모리를 포함하는 시스템의 단순화 된 블록도,
제2도와 2A도는 본 발명에 다른 방법에 의해 테스트될 수도 있는 메모리 카드의 어드레스 정보를 포함하는 데이터 흐름의 논리 블록도,
제3도는 본 발명의 양호한 실시예와 함께 사용하게 될 어드레스 버스 구조의 개략도.

Claims (3)

  1. 대규모 기억장치 배열체에서 어드레스 라인오류를 테스트하기 위한 방법에 있어서, 테스트 온 중의 비트로 형성된 어드레스에서 제1 메모리 워드내로 제1 비트 패턴을 기록하는 단계와, 테스트 오프 중의 비트로 형성된 어드레스에서 제2 메모리 워드내로 제2비트 패턴을 기록하는 단계와, 상기 두 어드레스 모두로부터 데이터를 판독하는 단계와, 영구 에러를 구성하는 예정된 수의 비트 에러에 대해 검사하는 단계와, 모든 어드레스 라인이 테스트될 때까지 상기 어드레스에서 각 비트에 대해 상기 단계를 반복하는 단계와, 테스트 오프 중의 상기 비트로 형성된 상기 어드레스에서 상기 제2메모리 워드에 상기 제1 데이타 패턴을 기록하는 단계와, 테스트 온 주의 상기 비트로 형성된 어드레스에서 상기 제1메모리 워드에 상기 제2데이타 패턴을 기록하는 단계와, 상기 어드레스 모두로부터의 데이터를 판독하는 단계와, 영구 에러를 구성하는 예정된 수의 비트 에러에 대해 검사하는 단계 및, 모든 어드레스 라인이 테스트될 때까지 상기 어드레스에서 각 비트에 대해 상기 단계를 반복하는 단계를 구비하는 것을 특징으로 하는 어드레스 라인 오류 테스트 방법.
  2. 제1항에 있어서, 상기 제1 비트 패턴은 모두 0인 패턴이며, 상기 제2비트 패턴은 모두 1인 패턴인 것을 특징으로 하는 어드레스 라인 오류 테스트 방법.
  3. 제1항에 있어서, 영구 에러를 구성하는 상기 예정된 수의 비트 에러는 멀티-카드 기억장치 배열체에서 각 카드에 대해 6개의 에러인 것을 특징으로 하는 어드레스 라인 오류 테스트 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880001348A 1987-02-13 1988-02-12 어드레스 라인 오류 테스트 방법 KR920001104B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/014,749 US4891811A (en) 1987-02-13 1987-02-13 Efficient address test for large memories
US014,749 1987-02-13

Publications (2)

Publication Number Publication Date
KR880010362A true KR880010362A (ko) 1988-10-08
KR920001104B1 KR920001104B1 (ko) 1992-02-01

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Country Status (14)

Country Link
US (1) US4891811A (ko)
EP (1) EP0281740B1 (ko)
JP (1) JP2519286B2 (ko)
KR (1) KR920001104B1 (ko)
CN (1) CN1008848B (ko)
AT (1) ATE83331T1 (ko)
AU (1) AU597140B2 (ko)
BR (1) BR8800244A (ko)
CA (1) CA1291269C (ko)
DE (1) DE3876459T2 (ko)
ES (1) ES2036223T3 (ko)
GB (1) GB2201016B (ko)
HK (1) HK35392A (ko)
SG (1) SG110891G (ko)

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CN113777911A (zh) * 2021-10-09 2021-12-10 中国北方车辆研究所 一种基于地址编码的控制器复合防错方法

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CN113777911B (zh) * 2021-10-09 2023-06-02 中国北方车辆研究所 一种基于地址编码的控制器复合防错方法

Also Published As

Publication number Publication date
EP0281740A2 (en) 1988-09-14
CA1291269C (en) 1991-10-22
KR920001104B1 (ko) 1992-02-01
DE3876459T2 (de) 1993-06-09
SG110891G (en) 1992-02-14
AU1035688A (en) 1988-08-18
EP0281740A3 (en) 1990-05-09
ES2036223T3 (es) 1993-05-16
CN1008848B (zh) 1990-07-18
CN88100490A (zh) 1988-08-24
GB2201016B (en) 1991-03-13
US4891811A (en) 1990-01-02
BR8800244A (pt) 1988-08-30
JPS63202000A (ja) 1988-08-22
ATE83331T1 (de) 1992-12-15
GB2201016A (en) 1988-08-17
JP2519286B2 (ja) 1996-07-31
HK35392A (en) 1992-05-29
EP0281740B1 (en) 1992-12-09
DE3876459D1 (de) 1993-01-21
GB8719405D0 (en) 1987-09-23
AU597140B2 (en) 1990-05-24

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