DE3876459T2 - Speicher und deren pruefung. - Google Patents

Speicher und deren pruefung.

Info

Publication number
DE3876459T2
DE3876459T2 DE8888100944T DE3876459T DE3876459T2 DE 3876459 T2 DE3876459 T2 DE 3876459T2 DE 8888100944 T DE8888100944 T DE 8888100944T DE 3876459 T DE3876459 T DE 3876459T DE 3876459 T2 DE3876459 T2 DE 3876459T2
Authority
DE
Germany
Prior art keywords
address
bits
card
test
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888100944T
Other languages
English (en)
Other versions
DE3876459D1 (de
Inventor
Kevin John Ash
Jack Harvey Derenburger
Raymond Lonnie Parsons
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3876459D1 publication Critical patent/DE3876459D1/de
Publication of DE3876459T2 publication Critical patent/DE3876459T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/1052—Bypassing or disabling error detection or correction
DE8888100944T 1987-02-13 1988-01-22 Speicher und deren pruefung. Expired - Fee Related DE3876459T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/014,749 US4891811A (en) 1987-02-13 1987-02-13 Efficient address test for large memories

Publications (2)

Publication Number Publication Date
DE3876459D1 DE3876459D1 (de) 1993-01-21
DE3876459T2 true DE3876459T2 (de) 1993-06-09

Family

ID=21767473

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888100944T Expired - Fee Related DE3876459T2 (de) 1987-02-13 1988-01-22 Speicher und deren pruefung.

Country Status (14)

Country Link
US (1) US4891811A (de)
EP (1) EP0281740B1 (de)
JP (1) JP2519286B2 (de)
KR (1) KR920001104B1 (de)
CN (1) CN1008848B (de)
AT (1) ATE83331T1 (de)
AU (1) AU597140B2 (de)
BR (1) BR8800244A (de)
CA (1) CA1291269C (de)
DE (1) DE3876459T2 (de)
ES (1) ES2036223T3 (de)
GB (1) GB2201016B (de)
HK (1) HK35392A (de)
SG (1) SG110891G (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5073891A (en) * 1990-02-14 1991-12-17 Intel Corporation Method and apparatus for testing memory
US5555249A (en) * 1991-09-18 1996-09-10 Ncr Corporation Non-destructive memory testing in computers
US5469443A (en) * 1993-10-01 1995-11-21 Hal Computer Systems, Inc. Method and apparatus for testing random access memory
US5479413A (en) * 1994-06-06 1995-12-26 Digital Equipment Corporation Method for testing large memory arrays during system initialization
US5539878A (en) * 1995-06-16 1996-07-23 Elonex Technologies, Inc. Parallel testing of CPU cache and instruction units
US20020091965A1 (en) * 2000-12-22 2002-07-11 Mark Moshayedi System and method for early detection of impending failure of a data storage system
US6842867B2 (en) 2001-01-26 2005-01-11 Dell Products L.P. System and method for identifying memory modules having a failing or defective address
US7308621B2 (en) 2002-04-30 2007-12-11 International Business Machines Corporation Testing of ECC memories
US7149941B2 (en) 2002-04-30 2006-12-12 International Business Machines Corporation Optimized ECC/redundancy fault recovery
US7085973B1 (en) * 2002-07-09 2006-08-01 Xilinx, Inc. Testing address lines of a memory controller
JP4299558B2 (ja) * 2003-03-17 2009-07-22 株式会社ルネサステクノロジ 情報記憶装置および情報処理システム
EP1629505B1 (de) * 2003-05-22 2009-07-15 Nxp B.V. Test von ram adressdekodierern auf widerstandsbehaftete leiterunterbrechungen
US8230275B2 (en) * 2005-05-26 2012-07-24 Hewlett-Packard Development Company, L.P. Use of parity bits to detect memory installation defects
CN101310343B (zh) * 2005-11-14 2014-04-30 三菱电机株式会社 存储器诊断装置
US7609561B2 (en) * 2006-01-18 2009-10-27 Apple Inc. Disabling faulty flash memory dies
CN100445963C (zh) * 2007-02-15 2008-12-24 华为技术有限公司 一种实现高可靠性空闲链表的方法及装置
EP2063432B1 (de) * 2007-11-15 2012-08-29 Grundfos Management A/S Verfahren zum Prüfen eines Arbeitsspeichers
DE102010027287A1 (de) * 2010-07-16 2012-01-19 Siemens Aktiengesellschaft Verfahren und Vorrichtung zum prüfen eines Hauptspeichers eines Prozessors
US9189313B2 (en) * 2012-08-27 2015-11-17 Kabushiki Kaisha Toshiba Memory system having NAND-type flash memory and memory controller with shift read controller and threshold voltage comparison module
CN104425040A (zh) * 2013-08-23 2015-03-18 辉达公司 用于测试存储器的方法和系统
CN113777911B (zh) * 2021-10-09 2023-06-02 中国北方车辆研究所 一种基于地址编码的控制器复合防错方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3727039A (en) * 1971-08-02 1973-04-10 Ibm Single select line storage system address check
JPS5138570B2 (de) * 1971-10-13 1976-10-22
NL7416755A (nl) * 1974-12-23 1976-06-25 Philips Nv Werkwijze en inrichting voor het testen van een digitaal geheugen.
US4100403A (en) * 1977-04-25 1978-07-11 International Business Machines Corporation Method and means for discriminating between systematic and noise-induced error in data extracted from word organized memory arrays
JPS5634198A (en) * 1979-08-27 1981-04-06 Nippon Telegr & Teleph Corp <Ntt> Releaving method of deficient bit of semiconductor memory
JPS5651678A (en) * 1979-10-03 1981-05-09 Nippon Telegr & Teleph Corp <Ntt> Testing method for memory element and pattern generator for test
DD148268A1 (de) * 1979-12-21 1981-05-13 Haupt Wolf Dieter Schaltungsanordnung zur blockweisen pruefung von hauptspeichern
JPS6019080B2 (ja) * 1980-10-17 1985-05-14 富士通株式会社 記憶装置のチェック方法
US4429389A (en) * 1981-05-26 1984-01-31 Burroughs Corporation Test pattern address generator
EP0088916B1 (de) * 1982-03-15 1985-11-21 Siemens-Albis Aktiengesellschaft Schaltungsanordnung zum Prüfen von elektrischen, insbesondere elektronischen Einrichtungen
JPS59180898A (ja) * 1983-03-31 1984-10-15 Hitachi Ltd 不良ビット救済方法
GB8401806D0 (en) * 1984-01-24 1984-02-29 Int Computers Ltd Data storage apparatus
JPS61137300A (ja) * 1984-12-06 1986-06-24 Sony Tektronix Corp メモリ検査方法
US4757503A (en) * 1985-01-18 1988-07-12 The University Of Michigan Self-testing dynamic ram
US4715034A (en) * 1985-03-04 1987-12-22 John Fluke Mfg. Co., Inc. Method of and system for fast functional testing of random access memories
JPS61278992A (ja) * 1985-06-04 1986-12-09 Toppan Moore Co Ltd 故障検査機能を備えたｉｃカ−ド
US4686456A (en) * 1985-06-18 1987-08-11 Kabushiki Kaisha Toshiba Memory test circuit

Also Published As

Publication number Publication date
JPS63202000A (ja) 1988-08-22
KR920001104B1 (ko) 1992-02-01
EP0281740A3 (en) 1990-05-09
GB2201016A (en) 1988-08-17
GB8719405D0 (en) 1987-09-23
US4891811A (en) 1990-01-02
EP0281740B1 (de) 1992-12-09
AU1035688A (en) 1988-08-18
EP0281740A2 (de) 1988-09-14
CA1291269C (en) 1991-10-22
CN1008848B (zh) 1990-07-18
SG110891G (en) 1992-02-14
KR880010362A (ko) 1988-10-08
DE3876459D1 (de) 1993-01-21
GB2201016B (en) 1991-03-13
BR8800244A (pt) 1988-08-30
AU597140B2 (en) 1990-05-24
JP2519286B2 (ja) 1996-07-31
ES2036223T3 (es) 1993-05-16
CN88100490A (zh) 1988-08-24
ATE83331T1 (de) 1992-12-15
HK35392A (en) 1992-05-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee