KR860009481A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법

Info

Publication number
KR860009481A
KR860009481A KR1019860003553A KR860003553A KR860009481A KR 860009481 A KR860009481 A KR 860009481A KR 1019860003553 A KR1019860003553 A KR 1019860003553A KR 860003553 A KR860003553 A KR 860003553A KR 860009481 A KR860009481 A KR 860009481A
Authority
KR
South Korea
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Application number
KR1019860003553A
Other languages
English (en)
Other versions
KR900004187B1 (ko
Inventor
가쯔야 오꾸무라
Original Assignee
가부시끼 가이샤 도오시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼 가이샤 도오시바 filed Critical 가부시끼 가이샤 도오시바
Publication of KR860009481A publication Critical patent/KR860009481A/ko
Application granted granted Critical
Publication of KR900004187B1 publication Critical patent/KR900004187B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019860003553A 1985-05-13 1986-05-07 반도체장치의 제조방법 KR900004187B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60100916A JPS61258453A (ja) 1985-05-13 1985-05-13 半導体装置の製造方法
JP60-100916 1985-05-13

Publications (2)

Publication Number Publication Date
KR860009481A true KR860009481A (ko) 1986-12-23
KR900004187B1 KR900004187B1 (ko) 1990-06-18

Family

ID=14286661

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860003553A KR900004187B1 (ko) 1985-05-13 1986-05-07 반도체장치의 제조방법

Country Status (5)

Country Link
US (1) US4914056A (ko)
EP (1) EP0215542B1 (ko)
JP (1) JPS61258453A (ko)
KR (1) KR900004187B1 (ko)
DE (1) DE3689371T2 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100216271B1 (ko) * 1996-07-30 1999-08-16 구본준 반도체 소자의 금속 배선 형성방법
KR100268558B1 (ko) * 1996-07-31 2000-10-16 아베 아키라 액정 표시 소자

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4824521A (en) * 1987-04-01 1989-04-25 Fairchild Semiconductor Corporation Planarization of metal pillars on uneven substrates
DE3735959A1 (de) * 1987-10-23 1989-05-03 Bbc Brown Boveri & Cie Mehrlagige duennschichtschaltung sowie verfahren zu deren herstellung
JPH02265243A (ja) * 1989-04-05 1990-10-30 Nec Corp 多層配線およびその形成方法
EP0393635B1 (en) * 1989-04-21 1997-09-03 Nec Corporation Semiconductor device having multi-level wirings
JPH04123458A (ja) * 1990-09-14 1992-04-23 Mitsubishi Electric Corp 半導体装置の製造方法
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
US5252503A (en) * 1991-06-06 1993-10-12 Lsi Logic Corporation Techniques for forming isolation structures
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
US5504375A (en) * 1992-03-02 1996-04-02 International Business Machines Corporation Asymmetric studs and connecting lines to minimize stress
KR950006343B1 (ko) * 1992-05-16 1995-06-14 금성일렉트론주식회사 반도체 장치의 제조방법
JP2853719B2 (ja) * 1992-06-08 1999-02-03 日本電気株式会社 半導体装置
JP3457348B2 (ja) * 1993-01-15 2003-10-14 株式会社東芝 半導体装置の製造方法
US5338702A (en) * 1993-01-27 1994-08-16 International Business Machines Corporation Method for fabricating tungsten local interconnections in high density CMOS
JP2727909B2 (ja) * 1993-03-26 1998-03-18 松下電器産業株式会社 金属配線の形成方法
US5471094A (en) 1994-02-24 1995-11-28 Integrated Device Technology, Inc. Self-aligned via structure
US5512514A (en) * 1994-11-08 1996-04-30 Spider Systems, Inc. Self-aligned via and contact interconnect manufacturing method
US5907177A (en) * 1995-03-14 1999-05-25 Matsushita Electric Industrial Co.,Ltd. Semiconductor device having a tapered gate electrode
US5726498A (en) * 1995-05-26 1998-03-10 International Business Machines Corporation Wire shape conferring reduced crosstalk and formation methods
US6191484B1 (en) 1995-07-28 2001-02-20 Stmicroelectronics, Inc. Method of forming planarized multilevel metallization in an integrated circuit
US5593919A (en) * 1995-09-05 1997-01-14 Motorola Inc. Process for forming a semiconductor device including conductive members
US5693568A (en) * 1995-12-14 1997-12-02 Advanced Micro Devices, Inc. Reverse damascene via structures
US6004874A (en) * 1996-06-26 1999-12-21 Cypress Semiconductor Corporation Method for forming an interconnect
US5898221A (en) * 1996-09-27 1999-04-27 Sanyo Electric Company, Ltd. Semiconductor device having upper and lower wiring layers
US6066548A (en) 1996-10-31 2000-05-23 Micron Technology, Inc. Advance metallization process
US6071810A (en) 1996-12-24 2000-06-06 Kabushiki Kaisha Toshiba Method of filling contact holes and wiring grooves of a semiconductor device
JPH11121612A (ja) * 1997-10-14 1999-04-30 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6222136B1 (en) * 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US6291891B1 (en) 1998-01-13 2001-09-18 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method and semiconductor device
FR2780202A1 (fr) * 1998-06-23 1999-12-24 St Microelectronics Sa Circuit integre a niveau de metallisation d'epaisseur variable
KR100295061B1 (ko) 1999-03-29 2001-07-12 윤종용 챔퍼가 형성된 실리사이드층을 갖춘 반도체소자 및 그 제조방법
KR100297738B1 (ko) * 1999-10-07 2001-11-02 윤종용 챔퍼가 형성된 금속 실리사이드층을 갖춘 반도체소자의 제조방법
US6992394B2 (en) * 2000-12-28 2006-01-31 Infineon Technologies Ag Multi-level conductive lines with reduced pitch
US6469392B2 (en) * 2000-12-28 2002-10-22 Infineon Technologies Ag Conductive lines with reduced pitch
EP1525630A2 (de) * 2002-07-29 2005-04-27 Siemens Aktiengesellschaft Elektronisches bauteil mit vorwiegend organischen funktionsmaterialien und herstellungsverfahren dazu
DE602004011062T2 (de) * 2003-06-24 2009-01-02 Cardinal Cg Co., Eden Prairie Konzentrationsmodulierte beschichtungen
SG11201601295TA (en) * 2013-08-28 2016-03-30 Inst Of Technical Education Multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device
EP4050644A1 (en) * 2021-02-24 2022-08-31 Imec VZW A method for forming an interconnect structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4894866A (ko) * 1972-03-15 1973-12-06
GB8316476D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
DE3331759A1 (de) * 1983-09-02 1985-03-21 Siemens AG, 1000 Berlin und 8000 München Integrierte halbleiterschaltung mit einer aus aluminium oder aus einer aluminium-legierung bestehenden mehrlagenverdrahtung und verfahren zu ihrer herstellung.
US4670091A (en) * 1984-08-23 1987-06-02 Fairchild Semiconductor Corporation Process for forming vias on integrated circuits
EP0175604B1 (en) * 1984-08-23 1989-07-19 Fairchild Semiconductor Corporation A process for forming vias on integrated circuits
US4614021A (en) * 1985-03-29 1986-09-30 Motorola, Inc. Pillar via process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100216271B1 (ko) * 1996-07-30 1999-08-16 구본준 반도체 소자의 금속 배선 형성방법
KR100268558B1 (ko) * 1996-07-31 2000-10-16 아베 아키라 액정 표시 소자

Also Published As

Publication number Publication date
KR900004187B1 (ko) 1990-06-18
DE3689371T2 (de) 1994-05-11
EP0215542A2 (en) 1987-03-25
JPS61258453A (ja) 1986-11-15
US4914056A (en) 1990-04-03
DE3689371D1 (de) 1994-01-20
EP0215542B1 (en) 1993-12-08
EP0215542A3 (en) 1988-09-28

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