KR860007741A - 반도체 기억장치의 제조방법 - Google Patents

반도체 기억장치의 제조방법

Info

Publication number
KR860007741A
KR860007741A KR1019860001429A KR860001429A KR860007741A KR 860007741 A KR860007741 A KR 860007741A KR 1019860001429 A KR1019860001429 A KR 1019860001429A KR 860001429 A KR860001429 A KR 860001429A KR 860007741 A KR860007741 A KR 860007741A
Authority
KR
South Korea
Prior art keywords
manufacturing
memory device
semiconductor memory
semiconductor
memory
Prior art date
Application number
KR1019860001429A
Other languages
English (en)
Other versions
KR900001249B1 (ko
Inventor
히데끼 아라까와
Original Assignee
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쓰 가부시끼가이샤 filed Critical 후지쓰 가부시끼가이샤
Publication of KR860007741A publication Critical patent/KR860007741A/ko
Application granted granted Critical
Publication of KR900001249B1 publication Critical patent/KR900001249B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/114—Nitrides of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
KR1019860001429A 1985-03-01 1986-02-28 반도체 기억장치의 제조방법 KR900001249B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60-41653 1985-03-01
JP60041653A JPS61222175A (ja) 1985-03-01 1985-03-01 半導体記憶装置の製造方法

Publications (2)

Publication Number Publication Date
KR860007741A true KR860007741A (ko) 1986-10-17
KR900001249B1 KR900001249B1 (ko) 1990-03-05

Family

ID=12614320

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860001429A KR900001249B1 (ko) 1985-03-01 1986-02-28 반도체 기억장치의 제조방법

Country Status (5)

Country Link
US (1) US4699690A (ko)
EP (1) EP0197284B1 (ko)
JP (1) JPS61222175A (ko)
KR (1) KR900001249B1 (ko)
DE (1) DE3671583D1 (ko)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0298430A3 (en) * 1987-07-08 1990-05-16 Hitachi, Ltd. Semiconductor device having a floating gate
US4833096A (en) * 1988-01-19 1989-05-23 Atmel Corporation EEPROM fabrication process
EP0325202A1 (de) * 1988-01-20 1989-07-26 Siemens Aktiengesellschaft Verfahren zur Herstellung von VLSI-Logikschaltungen in Poly-Silizium-Gate-NMOS-Technologie mit integriertem EEPROM-Speicher für Tunnelstromprogrammierung
FR2635408B1 (fr) * 1988-08-11 1992-04-10 Sgs Thomson Microelectronics Memoire de type eprom a haute densite d'integration
FR2635411A1 (fr) * 1988-08-11 1990-02-16 Sgs Thomson Microelectronics Memoire de type eprom a haute densite d'integration avec une organisation en damier, un facteur de couplage ameliore et une possibilite de redondance
FR2635409B1 (fr) * 1988-08-11 1991-08-02 Sgs Thomson Microelectronics Memoire de type eprom a haute densite d'integration possedant un facteur de couplage eleve, et son procede de fabrication
DE68915508T2 (de) * 1988-10-25 1994-12-15 Matsushita Electronics Corp Verfahren zur Herstellung einer nicht-flüchtigen Speicheranordnung.
US6373093B2 (en) 1989-04-28 2002-04-16 Nippondenso Corporation Semiconductor memory device and method of manufacturing the same
US5017979A (en) 1989-04-28 1991-05-21 Nippondenso Co., Ltd. EEPROM semiconductor memory device
JP2563683B2 (ja) * 1990-03-08 1996-12-11 松下電子工業株式会社 不揮発性半導体記憶装置およびその製造方法
IT1252214B (it) * 1991-12-13 1995-06-05 Sgs Thomson Microelectronics Procedimento per la definizione di porzioni di ossido sottile particolarmente per celle di memoria a sola lettura programmabili e cancellabile elettricamente.
US5316981A (en) * 1992-10-09 1994-05-31 Advanced Micro Devices, Inc. Method for achieving a high quality thin oxide using a sacrificial oxide anneal
US5362685A (en) * 1992-10-29 1994-11-08 Advanced Micro Devices, Inc. Method for achieving a high quality thin oxide in integrated circuit devices
US5910912A (en) * 1992-10-30 1999-06-08 International Business Machines Corporation Flash EEPROM with dual-sidewall gate
US5633186A (en) * 1995-08-14 1997-05-27 Motorola, Inc. Process for fabricating a non-volatile memory cell in a semiconductor device
DE19534780A1 (de) * 1995-09-19 1997-03-20 Siemens Ag Verfahren zum Erzeugen sehr kleiner Strukturweiten auf einem Halbleitersubstrat
US5904524A (en) * 1996-08-08 1999-05-18 Altera Corporation Method of making scalable tunnel oxide window with no isolation edges
US6127222A (en) * 1997-12-16 2000-10-03 Advanced Micro Devices, Inc. Non-self-aligned side channel implants for flash memory cells
US6624027B1 (en) * 2002-05-09 2003-09-23 Atmel Corporation Ultra small thin windows in floating gate transistors defined by lost nitride spacers
US7256449B2 (en) * 2003-05-20 2007-08-14 Samsung Electronics, Co., Ltd. EEPROM device for increasing a coupling ratio and fabrication method thereof
US20040232476A1 (en) * 2003-05-20 2004-11-25 Kang Sung-Taeg EEPROM cell structures having non-uniform channel-dielectric thickness and methods of making the same
KR100604850B1 (ko) * 2003-05-20 2006-07-31 삼성전자주식회사 균일하지 않은 채널 유전막 두께를 갖는 이이피롬 셀 구조및 그 제조방법
KR100546407B1 (ko) * 2004-04-30 2006-01-26 삼성전자주식회사 Ｅｅｐｒｏｍ 셀 제조방법

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US43943A (en) * 1864-08-23 Improvement in gathered fabrics
US4080718A (en) * 1976-12-14 1978-03-28 Smc Standard Microsystems Corporation Method of modifying electrical characteristics of MOS devices using ion implantation
US4224733A (en) * 1977-10-11 1980-09-30 Fujitsu Limited Ion implantation method
JPS5950214B2 (ja) * 1979-05-16 1984-12-07 松下電器産業株式会社 半導体装置の製造方法
US4313782A (en) * 1979-11-14 1982-02-02 Rca Corporation Method of manufacturing submicron channel transistors
DE3016050C2 (de) * 1980-04-25 1985-08-29 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung von Fotolackstrukturen für integrierte Halbleiterschaltungsanordnungen
US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
DE3174858D1 (en) * 1980-12-25 1986-07-24 Fujitsu Ltd Nonvolatile semiconductor memory device
JPS58130571A (ja) * 1982-01-29 1983-08-04 Hitachi Ltd 半導体装置
US4548834A (en) * 1982-05-31 1985-10-22 Nec Corporation Method of producing a Josephson tunnel barrier
US4507853A (en) * 1982-08-23 1985-04-02 Texas Instruments Incorporated Metallization process for integrated circuits
JPS60182171A (ja) * 1984-02-29 1985-09-17 Oki Electric Ind Co Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0197284A2 (en) 1986-10-15
DE3671583D1 (de) 1990-06-28
JPS61222175A (ja) 1986-10-02
US4699690A (en) 1987-10-13
JPS6364062B2 (ko) 1988-12-09
KR900001249B1 (ko) 1990-03-05
EP0197284A3 (en) 1988-09-14
EP0197284B1 (en) 1990-05-23

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E701 Decision to grant or registration of patent right
GRNT Written decision to grant
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