KR900000907A - 반도체기억장치의 제조방법 - Google Patents

반도체기억장치의 제조방법

Info

Publication number
KR900000907A
KR900000907A KR1019890001642A KR890001642A KR900000907A KR 900000907 A KR900000907 A KR 900000907A KR 1019890001642 A KR1019890001642 A KR 1019890001642A KR 890001642 A KR890001642 A KR 890001642A KR 900000907 A KR900000907 A KR 900000907A
Authority
KR
South Korea
Prior art keywords
manufacturing
memory device
semiconductor memory
semiconductor
memory
Prior art date
Application number
KR1019890001642A
Other languages
English (en)
Other versions
KR920008424B1 (ko
Inventor
나쓰오 아지까
Original Assignee
미쓰비시 뎅끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미쓰비시 뎅끼 가부시끼가이샤 filed Critical 미쓰비시 뎅끼 가부시끼가이샤
Publication of KR900000907A publication Critical patent/KR900000907A/ko
Application granted granted Critical
Publication of KR920008424B1 publication Critical patent/KR920008424B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
KR1019890001642A 1988-06-07 1989-02-13 반도체기억장치의 제조방법 KR920008424B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63141040A JPH07101713B2 (ja) 1988-06-07 1988-06-07 半導体記憶装置の製造方法
JP63-141040 1988-06-07

Publications (2)

Publication Number Publication Date
KR900000907A true KR900000907A (ko) 1990-01-31
KR920008424B1 KR920008424B1 (ko) 1992-09-28

Family

ID=15282843

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890001642A KR920008424B1 (ko) 1988-06-07 1989-02-13 반도체기억장치의 제조방법

Country Status (3)

Country Link
US (1) US4988635A (ko)
JP (1) JPH07101713B2 (ko)
KR (1) KR920008424B1 (ko)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0712062B2 (ja) * 1987-09-09 1995-02-08 三菱電機株式会社 半導体記憶装置の製造方法
JP2547622B2 (ja) * 1988-08-26 1996-10-23 三菱電機株式会社 不揮発性半導体記憶装置
JP2529885B2 (ja) * 1989-03-10 1996-09-04 工業技術院長 半導体メモリ及びその動作方法
US5182452A (en) * 1989-07-17 1993-01-26 Matsushita Electric Industrial Co. Ltd. Method for determining the presence of thin insulating films
JPH03245567A (ja) * 1990-02-23 1991-11-01 Toshiba Corp 半導体装置
US5280446A (en) * 1990-09-20 1994-01-18 Bright Microelectronics, Inc. Flash eprom memory circuit having source side programming
JP3124334B2 (ja) * 1991-10-03 2001-01-15 株式会社東芝 半導体記憶装置およびその製造方法
JPH04257270A (ja) * 1991-02-08 1992-09-11 Fujitsu Ltd 半導体記憶装置
US5723888A (en) * 1993-05-17 1998-03-03 Yu; Shih-Chiang Non-volatile semiconductor memory device
US5436480A (en) * 1993-02-22 1995-07-25 Yu; Shih-Chiang Integrated circuit interconnection programmable and erasable by a plurality of intersecting control traces
JP2682386B2 (ja) * 1993-07-27 1997-11-26 日本電気株式会社 半導体装置の製造方法
US5395779A (en) * 1994-04-08 1995-03-07 United Microelectronics Corporation Process of manufacture of split gate EPROM device
KR0144421B1 (ko) * 1994-07-18 1998-07-01 김주용 플레쉬 이.이.피.롬의 제조방법
KR0142604B1 (ko) * 1995-03-22 1998-07-01 김주용 플래쉬 이이피롬 셀 및 그 제조방법
US5550073A (en) * 1995-07-07 1996-08-27 United Microelectronics Corporation Method for manufacturing an EEPROM cell
KR100358141B1 (ko) * 1995-12-14 2003-01-29 주식회사 하이닉스반도체 이이피롬제조방법
DE19643185C2 (de) * 1996-10-18 1998-09-10 Siemens Ag Dual-Gate-Speicherzelle und Verfahren zur Herstellung einer nichtflüchtigen Speicherzelle
US5963806A (en) * 1996-12-09 1999-10-05 Mosel Vitelic, Inc. Method of forming memory cell with built-in erasure feature
US7375393B1 (en) * 2005-01-27 2008-05-20 National Semiconductor Corporation Non-volatile memory (NVM) retention improvement utilizing protective electrical shield

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6046554B2 (ja) * 1978-12-14 1985-10-16 株式会社東芝 半導体記憶素子及び記憶回路
JPS5780779A (en) * 1980-11-07 1982-05-20 Fujitsu Ltd Semiconductor non-volatile memory
GB2126788B (en) * 1982-03-09 1985-06-19 Rca Corp An electrically alterable nonvolatile floating gate memory device
US4513397A (en) * 1982-12-10 1985-04-23 Rca Corporation Electrically alterable, nonvolatile floating gate memory device
JPS6352478A (ja) * 1986-08-22 1988-03-05 Hitachi Ltd 半導体集積回路装置
US4775642A (en) * 1987-02-02 1988-10-04 Motorola, Inc. Modified source/drain implants in a double-poly non-volatile memory process
EP0417197A4 (en) * 1988-05-17 1992-07-08 Xicor, Inc Deposited tunneling oxide

Also Published As

Publication number Publication date
KR920008424B1 (ko) 1992-09-28
JPH07101713B2 (ja) 1995-11-01
JPH01309382A (ja) 1989-12-13
US4988635A (en) 1991-01-29

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