EP0417197A4 - Deposited tunneling oxide - Google Patents
Deposited tunneling oxideInfo
- Publication number
- EP0417197A4 EP0417197A4 EP19890907002 EP89907002A EP0417197A4 EP 0417197 A4 EP0417197 A4 EP 0417197A4 EP 19890907002 EP19890907002 EP 19890907002 EP 89907002 A EP89907002 A EP 89907002A EP 0417197 A4 EP0417197 A4 EP 0417197A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- silicon dioxide
- polysilicon
- oxide
- depositing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 230000005641 tunneling Effects 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 53
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims abstract description 34
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 25
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 25
- 238000000151 deposition Methods 0.000 claims abstract description 17
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000011261 inert gas Substances 0.000 claims abstract description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 238000000137 annealing Methods 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 2
- 229910052760 oxygen Chemical group 0.000 claims 2
- 239000001301 oxygen Chemical group 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 239000002210 silicon-based material Substances 0.000 claims 1
- 238000000354 decomposition reaction Methods 0.000 abstract description 2
- 230000007547 defect Effects 0.000 description 10
- 239000000758 substrate Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Abstract
A semiconductor device and a method for depositing a tunneling oxide layer between two conducting layers utilizing a low pressure, low temperature chemical vapor deposition (LPCVD) process is disclosed wherein tetraethylorthosilicate (TEOS) is preferably used. As applied to an electrically erasable programmable read only memory (EEPROM) device having polysilicon layers, the device is fabricated by forming a first layer of polysilicon (24), patterned as desired. A layer of silicon dioxide is then deposited by decomposition of TEOS to form the tunneling oxide to a predetermined thickness (32). If enhanced emission structures are desired, a layer of relatively thin tunneling oxide may be grown on the first layer of polysilicon. The oxide layer is then annealed and densified, preferably using steam and an inert gas at a specific temperature. A second layer of polysilicon is then formed on top of the tunneling oxide (26).
Description
DEP05ITED TO NET.INH OXTDR FIELD OF THE INVENTION
This invention relates to the field of integrated circuit processing and more specifically to a method of depositing tunneling oxide in an electrically eraseable read-only memory device. Background of the Invention
EEPROM devices are nonvolatile memory devices in which the presence or absence of charge on a floating gate electrode indicates a binary one or zero. One EEPROM device is described in United States Patent No. 4,579,706, entitled "Nonvolatile Electrically Alterable Memory". This patent is herein incorporated by reference. In this type of EEPROM device, the floating gate electrode is electrically insulated from the other electrodes of the device by one or more layers of tunneling oxide. Electrical charge is transferred to the floating gate by placing a voltage on a programming electrode which is sufficient to cause electrons to tunnel through the tunneling oxide to the floating gate electrode. In EEPROM devices, the tunneling oxide can conduct only a limited amount of charge under the high fields imposed across the oxide during tunneling before the tunneling oxide fails or breaks down, thus limiting the number of programming cycles. In some tunneling elements in an EEPROM array, this failure may occur in less than approximately 10,000 programming cycles, depending on the uniformity and intrinsic defect density of the tunneling oxide layer ot layers.
The characteristics of the tunneling oxide layer are critical to the life and operation of an EEPROM device. In prior EEPROM devices, tunneling oxides are produced by growing an oxide using a thermal oxidation process. However, with this type of process, the oxide defect density is quite high, which causes a
large number of early breakdown failures. As presently understood, this is because any defects in the underlying silicon may propagate into the silicon dioxide layer as it is grown. Furthermore, during the thermal oxidation process, the tunneling oxide develops a high level of stress. As presently understood, -this phenomena causes defects resulting in early or premature failures in the oxide during tunneling, thus further limiting the life of the device. No technique is known for thermally growing a low-stress tunneling oxide, while providing an oxide layer with substantially zero defects. Summary of UL£_Iny tion Briefly described, the present invention contemplates a method and means of depositing a tunneling oxide layer between two conductors with a low pressure, low temperature chemical vapor deposition (LPCVD) process. Preferably, tetraethylorthosilicate (TEOS) is used for this deposition process. Where the present method is used in an EEPROM device and polysilicon layers are used for forming the device, the deposited oxide iε formed as follows. According to the present invention, a first layer of polysilicon is deposited and patterned as desired. A layer of silicon dioxide iε then deposited by a decomposition of tetraethylortnoεilicate to form a predetermined thickness of tunneling oxide on the surface of the polysilicon. The oxide layer formed from the deposited tetraethylorthosilicate is then thermally annealed and densified. Preferably, this iε performed using a mixture of steam and an inert gas, such as argon, at a predetermined temperature. The process may be repeated where more than one tunneling layer is desired. Where necessary, prior to depositing the tetraethyl¬ orthosilicate, where enhanced emiεεion structures are desired on the surface of the polysilicon, a layer of
relatively thin oxide thermal oxide may be grown on the surface of the polysilicon.
Accordingly, it is an object of the present invention to provide a tunneling oxide in an EEPROM device which may be deposited with a low pressure chemical vapor deposition process.
It iε another object of the present invention to improve the useful lifetime of an EEPROM device. 0 It is yet another object of the present invention to improve the yield in EEPROM processing.
It is another object of the present invention to improve the reliability of an EEPROM device. It is yet another object of the present 5 invention to produce a tunneling dielectric that is not limited by the underlying defect density of the material on which the oxide layer is being formed.
It iε yet another object of the present invention to produce a tunneling dielectric having 0 minimum stress. i iief De-S-Cript cn of the D awing
These and other objects will be apparent through the description below and the accompanying drawings in which: :; Figure 1 is a cutaway view of a three layer thick-oxide EEPROM device constructed in accordance with the present invention; and
Figures 2 is a flow diagram detailing a process for manufacturing one of the tunneling oxide 0 regions of the device of Figure 1. Detailed Description of the Invention
Referring now to Figure 1, there iε shown a cutaway view of a three layer polysilicon device which may advantageously employ the tunneling oxide layer of ^ the present invention. The operation and manufacture of the device of Figure 1 is substantially described in U.S. Patent No. 4,599,706, the difference being the
substitution of the present deposited oxide for the thermal oxide described in the above U.S. patent.
The EEPROM device 10 of Figure 1 is formed on a substrate 12 which comprises a "p"-type semiconductor material. Two n+ regions 20, 22 are diffused on opposing ends of the substrate. An n- region 24 is diffused in a central upper region of substrate 12. The n+ source, drain regions 20, 22 and n- diffusion 24 may be formed using a conventional well known αiffusion process. The EEPROM device 10 further includes a polysilicon electrode 24 which iε iεolated from substrate 12 by oxide region 30 and polysilicon electrodes 26 and 28 which are separated from the substrate, and each other by tunneling oxide regions or elements 32 and 34. In prior EEPROM devices, the oxide used for forming these tunneling elements 32, 34 was thermally grown, which iε believed to cause streεs and defects in tunneling oxide elements 32, 34 because defects from the underlying silicon substitute or pclysilicon region may propagate into the tunneling oxide.
The present invention contemplates the use of a low pressure chemical vapor deposition process to form elements 32, 34. In a thermal oxidation process, once the tunneling oxides are grown, subsequent thermal procesεing causes thermal stress in the oxide, thus causing additional breakdown and charge trap-up problems in the device. The present invention contemplates the use of a low temperature process to minimize thermal oxide growth during the processing of the device, which significantly reduces streεε and thereby increases the useful life of the device. This feature has also been found to enhance electron tunneling in the resulting device. Furthermore, the low pressure chemical vapor deposition process used according to the present invention for forming an oxide
layer is believed to avoid the propagation of defects into the oxide from the underlying substrate or polysilicon. Atmospheric deposition of silicon has been attempted in the paεt using silicon rich Siθ2 in a chemical vapor deposition process. One such process is described in an article entitled "Silicon - Rich Siθ2 and Thermal Siθ2 Dual Dielectric for Yield Improvement and High Capacitance", IEEE Transactions on Electron eviceε, Vol. ED-30, No. 8, P. 894, August 1983. The process described in this publication is experimental and has been found to be inadequate for use in rr.anufacturing tunneling oxides because silicon rich Siθ2 iε not a stoichiometric compound and thus contains impurities which affect the uniformity of the deposited cxide. The uεe of an atmospheric deposition also creates large variations in thickness of the resulting layer and, therefore, silicon rich Siθ2 has only been used for relatively thick layers. Furthermore, although the added silicon in the above procesε provides a form of enhancement for electron tunneling through the dielectric formed by this process, it's not as efficient aε the formation of a textured surface on the underlying silicon substrate or polysilicon conductive layer. This is because the silicon rich Siϋ2 apparently forms regions or balls of silicon in the silicon dioxide near the surface therof but spread out. Thus, they are not conductive with each other or with the surface of the dielectric and so are less efficient aε enhanced emisεion structures as compared with the textured surface of a polysilicon layer.
Other commonly used deposited oxide processes have been developed in the past for forming oxide layers between metal layers in the range of .5 microns to several microns or for filling trenches. However,
theεe processes have been found to be inadequate for forming thinner layers (on the order of 2000 or less Angstroms) such as are required for tunneling oxide elements, because these processes have poor uniformity and suffer from low breakdown voltages at such thicknesses. One such process employs tetraethyl¬ orthosilicate (TEOS) which is available from the J.C. Schumacher Co. and has typically been used for thick oxide procesεes. This material is also called tetraethyloxyεilane.
The present invention overcomes the above problem by modifying the known deposited oxide process using a denεification or annealing step on the TEOS deposited oxide during processing. It has been found that by exposing the TEOS deposited oxide to a steam and inert gas mixture at a relatively high temperature, the properties of the TEOS oxide are modified to equal or exceed those of thermally grown oxides. The resulting material has substantially improved dielectric properties and the resulting material is substantially free of leakage and does not break down in the presence of a strong electric field. It is believed that this annealing process provides more uniform molecular bonding by permitting greater viscous flow in the TEOS deposited oxide thus reducing or eliminating defects in the resulting dielectric layer. Since this steam ambient at the desired annealing temperature grows oxide at a relatively fast rate, which would thereby increase the thickness of the dielectric layer, the inert gas provides a partial pressure which is used to slow this undesired oxide growth rate while allowing the annealing process to proceed. The process of the present invention has been found to increase the total charge conducted through the dielectric layer by at least one order of magnitude before catastrophic breakdown, while at the same time
providing a dramatic improvement in processing yields.
Referring now to Figures 2A and 2B, the process 200 begins with step 202 wherein an initial layer of gate oxide, approximately 400 Angstroms thick is deposited on a substrate. This oxide layer may be formed with a conventional thermal oxide process. In step 204 the first layer of polysilicon is formed with a conventional polysilicon deposition process. The first layer of polysilicon is deposited approximately 4000 Angεtronε thick. In step 206, the first layer of polysilicon is doped to render the polysilicon layer conductive. Tne first layer of polysilicon may then be masked in step 210 and etched in step 212 using either a reactive ior. etcn or wet etch process. In the preferred practice of the present invention, it iε desirable that the surface of each tunneling region be somewhat irregular to promote electron tunneling. These surface irregularities or microtextured surfaces are formed by thermally oxidizing the surface of the polysilicon layer with step 216. The thermal oxide of step 216 iε then etched back to leave a layer of oxide approximately 150 Angstroms thick. The tunneling oxide layer is then formed by steps 220, 222 and 223. In step 220, oxide iε deposited over the relatively thin layer of thermal oxide using a low pressure chemical vapor deposition system with TEOS as the preferred yaseous medium. The TEOS gas is supplied via a bubbler by direct pull with the furnace temperature at approximately 600°C. The deposition rate is controlled primarily by the bubbler and furnace temperatures. The oxide is deposited to create an oxide layer of between 250 and 2000 Angstroms thick. This oxide layer is then annealed in steps 222 and 223. The annealing process of step 222 is done by exposing the TEOS produced silicon dioxide layer to a gaseous mixture of steam and argon at a temperature
range of approximately 700-1100°C for approximately 1-5 minutes. This is preferrably followed by further thermal annealing in a solely nitrogen ambient at step 223 to prevent further oxidation of the surface. This is performed at the same approximate temperature range for between 2 and 20 minutes. Other annealing processes, such as rapid optical annealing may also be employed at different temperatures and timing aε is known in the art for thick deposited oxide layers. The process is continued at step 224 wherein the next layer of polysilicon, approximately 4000-6000 Angstroms thick, is deposited by conventional means. The second layer of polysilicon is then doped in step 226. The second layer of polysilicon is then masked for further processing in step 230. Depending on whether additional layers of polysilicon are required, decision 232 either routeε the process back to step 212 or exits the process at step 234. The resulting structure may then be metalized and finished according to conventional means.
In summary, an improved method and means for making a tunneling oxide using TEOS deposited silicon dioxide has been described. Accordingly, other uses and modifications will be apparent to a person of ordinary skill in the art without departing from the scope of the present invention.
Claims
WHAT IS CLAIMED IS:
1. A method of manufacturing a tunneling oxide comprising the steps of: depositing a layer of silicon dioxide over a conductive structure using a low pressure chemical vapor deposition process with a silicon and oxygen bearing vapor at a temperature between 450° and 1000° C to provide a layer of a thickness between 50 and 2000 Angstroms; and forming a conductive structure on top of said silicon dioxide layer.
2. The method of Claim 1 wherein said silicon and oxygen bearing vapor comprises tetraethyl¬ orthosilicate.
3. The method of Claim 1 further including the step of annealing said silicon dioxide layer prior to the forming of said second conductive layer.
4. The method of Claim 2 wherein said annealing step comprises the step of exposing said silicon dioxide layer to a mixture of steam and an inert gas at a temperature of between 700°C and 1100°C.
5. The method of Claim 4 further comprising the step of thermally annealing said silicon dioxide layer in a solely nitrogen ambient at a temperature of between 700°C and 1100°C for between one and five minutes.
6. A method of depositing tunneling oxide in a EEPROM device comprising the steps of:
(a) depositing a layer of conductive material in a desired pattern;
(b) depositing a layer of silicon dioxide over said conductive material in a predetermined thickness of less then 2000 Angstroms with a low pressure chemical vapor deposition process; and
(c) annealing said silicon dioxide layer with a mixture of steam and an inert gas at a predetermined temperature.
7. A method of depositing a relatively thin tunneling dielectric in a semiconductor device comprising the steps of:
(a) thermally growing a relatively thin layer of oxide over a silicon material; and
10 (b) depositing a layer of silicon dioxide over said thermal oxide layer in a predetermined thickness less than 2000 Angstroms with a low pressure chemical vapor deposition procesε.
8. The method of Claim 7 further including i annealing εaid deposited silicon dioxide layer with a mixture of steam and an inert gaε at a predetermined temperature.
9. A method of depositing tunneling oxide in a EEPROM device comprising the εtepε of: o (a) forming a layer of polysilicon in a deεired pattern; and
(b) depositing a layer of silicon dioxide over said polysilicon layer in a predetermined thicknesε less then 2000 Angstroms with a low pressure 5 chemical vapor deposition procesε.
10. The method of Claim 9 further including annealing said silicon dioxide layer with a mixture of steam and an inert gas at a predetermined temperature.
11. A method of depositing tunneling oxide in 0 an EEPROM device comprising the steps of:
(a) forming a layer of polysilicon in a desired pattern;
(b) growing a layer of thermal oxide over said layer of polysilicon; 5 (c) etching said layer of thermal oxide to provide a thermal oxide layer of a deεired thickness;
(d) depositing a layer of silicon dioxide over said etched layer of thermal oxide in a predetermined thickness less than 2000 Anstroms thick with a low pressure chemical vapor deposition process using tetraethylorthosilicate as the gaseous medium;
(e) annealing and densifying said layer of silicon dioxide by exposing said layer of silicon dioxide to a mixture of steam and an inert gas at a temperature of between 700° and 1100°C; and
(f) further annealing said layer of silicon dioxide by exposing said layer of silicon dioxide to nitrogen at a temperature of between 700° and 1100°C.
12. The method of claim 11 further including the step of: forming a layer of polysilicon over said deposited layer of silicon dioxide.
13. An improved tunneling region for use with an integrated circuit comprising: a first layer of polysilicon a layer of thermal oxide formed over said first layer of polysilicon a layer of deposited silicon dioxide formed over said layer of thermal oxide in a thickness less than 2000 Angstroms thick; and a second layer of polysilicon formed over said layer of deposited silicon dioxide.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US19576688A | 1988-05-17 | 1988-05-17 | |
| US195766 | 1988-05-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0417197A1 EP0417197A1 (en) | 1991-03-20 |
| EP0417197A4 true EP0417197A4 (en) | 1992-07-08 |
Family
ID=22722714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP19890907002 Ceased EP0417197A4 (en) | 1988-05-17 | 1989-05-16 | Deposited tunneling oxide |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0417197A4 (en) |
| JP (1) | JP2703638B2 (en) |
| KR (1) | KR0165856B1 (en) |
| WO (1) | WO1989011731A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07101713B2 (en) * | 1988-06-07 | 1995-11-01 | 三菱電機株式会社 | Method of manufacturing semiconductor memory device |
| US5153691A (en) * | 1989-06-21 | 1992-10-06 | Xicor, Inc. | Apparatus for a dual thickness floating gate memory cell |
| US5593494A (en) * | 1995-03-14 | 1997-01-14 | Memc Electronic Materials, Inc. | Precision controlled precipitation of oxygen in silicon |
| JP3245136B2 (en) * | 1999-09-01 | 2002-01-07 | キヤノン販売株式会社 | Method of improving film quality of insulating film |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4613956A (en) * | 1983-02-23 | 1986-09-23 | Texas Instruments Incorporated | Floating gate memory with improved dielectric |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3934060A (en) * | 1973-12-19 | 1976-01-20 | Motorola, Inc. | Method for forming a deposited silicon dioxide layer on a semiconductor wafer |
| JPS60148168A (en) * | 1984-01-13 | 1985-08-05 | Seiko Instr & Electronics Ltd | Semiconductor nonvolatile memory |
| US4526631A (en) * | 1984-06-25 | 1985-07-02 | International Business Machines Corporation | Method for forming a void free isolation pattern utilizing etch and refill techniques |
| JPS61136274A (en) * | 1984-12-07 | 1986-06-24 | Toshiba Corp | Semiconductor device |
| US4763177A (en) * | 1985-02-19 | 1988-08-09 | Texas Instruments Incorporated | Read only memory with improved channel length isolation and method of forming |
| US4713677A (en) * | 1985-02-28 | 1987-12-15 | Texas Instruments Incorporated | Electrically erasable programmable read only memory cell including trench capacitor |
| US4599706A (en) * | 1985-05-14 | 1986-07-08 | Xicor, Inc. | Nonvolatile electrically alterable memory |
-
1989
- 1989-05-16 KR KR1019900700109A patent/KR0165856B1/en not_active IP Right Cessation
- 1989-05-16 JP JP1506338A patent/JP2703638B2/en not_active Expired - Lifetime
- 1989-05-16 EP EP19890907002 patent/EP0417197A4/en not_active Ceased
- 1989-05-16 WO PCT/US1989/002111 patent/WO1989011731A1/en not_active Application Discontinuation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4613956A (en) * | 1983-02-23 | 1986-09-23 | Texas Instruments Incorporated | Floating gate memory with improved dielectric |
Non-Patent Citations (2)
| Title |
|---|
| JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B. vol. 5, no. 6, November 1987, NEW YORK US pages 1555 - 1563; F.S. BECKER ET AL.: 'Low-pressure deposition of high-quality SiO2 films by pyrolysis of tetraethylorthosilicate.' * |
| See also references of WO8911731A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| KR0165856B1 (en) | 1999-02-01 |
| JP2703638B2 (en) | 1998-01-26 |
| WO1989011731A1 (en) | 1989-11-30 |
| KR900702567A (en) | 1990-12-07 |
| JPH03505145A (en) | 1991-11-07 |
| EP0417197A1 (en) | 1991-03-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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